View MCP47FEB02A0-EST_8693011.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

? 2015 microchip technology inc. ds20005375a-page 1 mcp47febxx features operating voltage range: - 2.7v to 5.5v - full specifications - 1.8v to 2.7v - reduced device specifications output voltage resolutions: - 8-bit: mcp47feb0x (256 steps) - 10-bit: mcp47feb1x (1024 steps) - 12-bit: mcp47feb2x (4096 steps) rail-to-rail output fast settling time of 6 s (typical) dac voltage reference source options: - device v dd -external v ref pin (buffered or unbuffered) - internal band gap (1.22v typical) output gain options: - unity (1x) - 2x (when not using internal v dd as voltage source) nonvolatile memory (eeprom): - user-programmed power-on reset (por)/brown-out reset (bor) output setting recall and device configuration bits - auto recall of saved dac register setting - auto recall of saved device configuration (voltage reference, gain, power-down) power-on/brown-out reset protection nonvolatile memory write protect (wp ) bit power-down modes: - disconnects output buffer (high impedance) - selection of v out pull-down resistors (100 k ? or 1 k ? ) low power consumption: - normal operation: <180 a (single), 380 a (dual) - power-down operation: 650 na typical - eeprom write cycle (1.9 ma maximum) i 2 c? interface: - slave address options: four predefined addresses or user programmable (all 7 bits) - standard (100 kbps), fast (400 kbps), and high-speed (up to 3.4 mbps) modes package types: 8-lead tssop extended temperature range: -40c to +125c package types general description the mcp47febxx are single- and dual-channel 8-bit, 10-bit, and 12-bit buffered voltage output digital-to- analog converters (dac) with nonvolatile memory and an i 2 c serial interface. the v ref pin, the device v dd or the internal band gap voltage can be selected as the dacs reference voltage. when v dd is selected, v dd is connected internally to the dac reference circuit. when the v ref pin is used, the user can select the output buffers gain to be 1 or 2. when the gain is 2, the v ref pin voltage should be limited to a maximum of v dd /2. these devices have a two-wire i 2 c-compatible serial interface for standard (100 khz), fast (400 khz) or high-speed (1.7 mhz and 3.4 mhz) modes. applications set point or offset trimming sensor calibration low-power portable instrumentation pc peripherals data acquisition systems motor control mcp47febx1 tssop single v out0 v ref0 nc scl lat0/hvc 1 2 3 4 8 7 6 5 v ss sda v dd mcp47febx2 tssop dual v out0 v ref ( 1 ) v out1 scl lat ( 1 ) /hvc 1 2 3 4 8 7 6 5 v ss sda v dd note 1: this pins signal can be connected to dac0 and/or dac1. 8-/10-/12-bit single/dual vo ltage output nonvolatile digital-to-analog converters with i 2 c? interface downloaded from: http:///
mcp47febxx ds20005375a-page 2 ? 2015 microchip technology inc. mcp47febx1 device block diagram (single-channel output) power-up/ brown-out control v dd v ss i 2 c? serial interface module and control logic (wiperlock? technology) memory (32x16) dac0 (vol and nv) v ref0 op amp gain v out0 lat0/hvc resistor ladder v ss pd1:pd0 and vref1:vref0 vref1:vref0 + - v dd sda scl band gap (1.22v) pd1:pd0 vref1:vref0 v dd v bg pd1:pd0 1k ? 100 k ? vref (vol and nv) power-down (vol and nv) gain (vol and nv) status (vol) slave address (nv) ( 1 ) and pd1:pd0 note 1: if internal band gap is selected, this buffer has a 2x gain. if the g bit = 1 , this is a total gain of 4. downloaded from: http:///
? 2015 microchip technology inc. ds20005375a-page 3 mcp47febxx mcp47febx2 device block diagram (dual-channel output) device features power-up/ brown-out control v dd v ss i 2 c? serial interface module and control logic (wiperlock? technology) v ref lat/hvc resistor ladder op amp gain v out1 resistor ladder intvr1 pd1:pd0 and vref1:vref0 vref1:vref0 + - v dd pd1:pd0 and vref1:vref0 vref1:vref0 + - v dd sda scl band gap (1.22v) band gap (1.22v) pd1:pd0 v dd v bg v dd v ss v ss pd1:pd0 op amp gain v out0 1k ? 100 k ? 1k ? 100 k ? memory (32x16) dac0 and 1 (vol & nv) vref (vol and nv) power-down (vol and nv) gain (vol and nv) status (vol) slave addr (nv) vref1:vref0 and pd1:pd0 vref1:vref0 and pd1:pd0 pd1:pd0 pd1:pd0 ( 1 ) ( 1 ) note 1: if internal band gap is selected, this buffer has a 2x gain, if the g bit = 1 , this is a total gain of 4. device # of channels resolution (bits) control interface dac output por/bor setting ( 1 ) # of vref inputs internal band gap ? # of lat inputs memory specified operating range (v dd ) mcp47feb01 1 8 i 2 c? 7fh 1 yes 1 eeprom 1.8v to 5.5v mcp47feb11 1 10 i 2 c 1ffh 1 yes 1 eeprom 1.8v to 5.5v mcp47feb21 1 12 i 2 c 7ffh 1 yes 1 eeprom 1.8v to 5.5v mcp47feb02 2 8 i 2 c 7fh 1 yes 1 eeprom 1.8v to 5.5v mcp47feb12 2 10 i 2 c 1ffh 1 yes 1 eeprom 1.8v to 5.5v mcp47feb22 2 12 i 2 c 7ffh 1 yes 1 eeprom 1.8v to 5.5v note 1: the factory default value. the dac output por/bor value can be modified via the nonvolatile dac out- put register(s). downloaded from: http:///
mcp47febxx ds20005375a-page 4 ? 2015 microchip technology inc. notes: downloaded from: http:///
? 2015 microchip technology inc. ds20005375a-page 5 mcp47febxx 1.0 electrical characteristics absolute maximum ratings (?) voltage on v dd with respect to v ss ......................................................................................................... -0.6v to +6.5v voltage on all pins with respect to v ss ............................................................................................... -0.6v to v dd +0.3v input clamp current, i ik (v i < 0, v i > v dd , v i > v pp on hv pins) .......................................................................... 20 ma output clamp current, i ok (v o < 0 or v o > v dd )...................................................................................................20 ma maximum current out of v ss pin (single) ..........................................................................................................50 ma (dual)...........................................................................................................100 ma maximum current into v dd pin (single) ..........................................................................................................50 ma (dual)...........................................................................................................100 ma maximum current sourced by the v out pin ............................................................................................................20 ma maximum current sunk by the v out pin..................................................................................................................20 ma maximum current sunk by the v ref pin .................................................................................................................125 a maximum input current source/sunk by sda, scl pins ............................................................................ ..............2 ma maximum output current sunk by sda output pin ................................................................................. ................25 ma total power dissipation ( 1 ) ............................................................................................................................... .....400 mw package power dissipation (t a = +50c, t j = +150c) tssop-8........................................................................................................................ ...........................700 mw esd protection on all pins ???????????????????????????????????????????????????????????????????????????????????????????????????? ????????????????????????????????????? 4 kv (hbm) ???????????????????????????????????????????????????????????????????????????????????????????????????? ???????????????????????????????????????????????????????????????????????? 400v (mm) ???????????????????????????????????????????????????????????????????????????????????????????????????? ??????????????????????????????????????????????????????????????????????? 2 kv (cdm) latch-up (per jedec jesd78a) @ +125c ......................................................................................... ............ 100 ma storage temperature ............................................................................................................ ...................-65c to +150c ambient temperature with power applied ........................................................................................ .......-55c to +125c soldering temperature of leads (10 seconds) .................................................................................... ................... +300c maximum junction temperature (t j ) .................................................................................................................... +150c note 1: power dissipation is calculated as follows: p dis = v dd x {i dd - ? i oh } + ? {(v dd Cv oh ) x i oh } + ? (v ol x i ol ) ? notice: stresses above those listed under maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operational listings of this specification is not implied. exposure to maximum rating conditions for extended periods may affect device reliability. downloaded from: http:///
mcp47febxx ds20005375a-page 6 ? 2015 microchip technology inc. dc characteristics dc characteristics standard operating conditions (unless otherwise specified) operating temperature C40c ? t a ? +125c (extended) all parameters apply across the specified operating ranges unless noted. v dd = +2.7v to 5.5v, v ref = +2.048v to v dd , v ss = 0v, gx = 0 , r l = 5 k ? from v out to gnd, c l = 100 pf. typical specifications represent values for v dd = 5.5v, t a = +25c. parameters sym. min. typ. max. units conditions supply voltage v dd 2.7 5.5 v 1.8 2.7 v dac operation (reduced analog specifications) and serial interface v dd voltage (rising) to ensure device power-on reset v por/bor 1.7 v ram retention voltage (v ram ) < v por v dd voltages greater than v por/bor limit ensure that device is out of reset. v dd rise rate to ensure power-on reset v ddrr ( note 3 )v / m s high-voltage commands voltage range (hvc pin) v hv v ss 12.5 v the hvc pin will be at one of three input levels (v il , v ih or v ihh ) ( 1 ) high-voltage input entry voltage v ihhen 9.0 v threshold for entry into wiperlock? technology high-voltage input exit voltage v ihhex v dd +0.8v v ( note 1 ) power-on reset to out- put-driven delay t pord 2 5 5 0 sv dd rising, v dd > v por note 1 this parameter is ensured by design. note 3 por/bor voltage trip point is not slope dependent. hysteresis implemented with time delay. downloaded from: http:///
? 2015 microchip technology inc. ds20005375a-page 7 mcp47febxx dc characteristics (continued) dc characteristics standard operating conditions (unless otherwise specified) operating temperature C40c ? t a ? +125c (extended) all parameters apply across the specified operating ranges unless noted. v dd = +2.7v to 5.5v, v ref = +2.048v to v dd , v ss = 0v, gx = 0 , r l = 5 k ? from v out to gnd, c l = 100 pf. typical specifications represent values for v dd = 5.5v, t a = +25c. parameters sym. min. typ. max. units conditions supply current i dd 500 a single serial interface active (not high-voltage command), vrxb:vrxa = 01 ( 6 ) , v out is unloaded, v dd = 5.5v volatile dac register = 000h i 2 c?: f scl = 3.4 mhz 700 a dual 400 a single serial interface active ( 2 ) (not high-voltage command), vrxb:vrxa = 10 ( 4 ) , v out is unloaded, v ref = v dd = 5.5v volatile dac register = 000h i 2 c: f scl = 3.4 mhz 550 a dual 180 a single serial interface inactive ( 2 ) (not high-voltage command), vrxb:vrxa = 00 , scl = sda = v ss , v out is unloaded, volatile dac register = 000h 380 a dual 180 a single serial interface inactive ( 2 ) (not high-voltage command), vrxb:vrxa = 11 , v ref = v dd , scl = sda = v ss , v out is unloaded, volatile dac register = 000h 380 a dual 1.9 ma ee write current v ref = v dd = 5.5v (after write, serial interface is inactive), write all 0 s to nonvolatile dac 0 (address 10h), v out pins are unloaded. 145 180 a single hvc = 12.5v (high-voltage command), serial interface inactive v ref = v dd = 5.5v, lat/hvc = v ihh , dac registers = 000h, v out pins are unloaded. 260 400 a dual power-down current i ddp 0.65 3.8 a pdxb:pdxa = 01 ( 5 ) , v out not connected note 2 this parameter is ensured by characterization. note 4 supply current is independent of current through the resistor ladder in mode vrxb:vrxa = 10 . note 5 the pdxb:pdxa = 01 , 10 , and 11 configurations should have the same current. note 6 by design, this is worst-case current mode. downloaded from: http:///
mcp47febxx ds20005375a-page 8 ? 2015 microchip technology inc. dc characteristics (continued) dc characteristics standard operating conditions (unless otherwise specified) operating temperature C40c ? t a ? +125c (extended) all parameters apply across the specified operating ranges unless noted. v dd = +2.7v to 5.5v, v ref = +2.048v to v dd , v ss = 0v, gx = 0 , r l = 5 k ? from v out to gnd, c l = 100 pf. typical specifications represent values for v dd = 5.5v, t a = +25c. parameters sym. min. typ. max. units conditions resistor ladder resistance r l 100 140 180 k ? 1.8v ? v dd ? 5.5v, v ref ? 1.0v ( 7 ) resolution (# of resistors and # of taps) (see c.1 resolution ) n 256 taps 8-bit no missing codes 1024 ta p s 10-bit no missing codes 4096 ta p s 12-bit no missing codes nominal v out match ( 12 ) |v out - v outmean | /v outmean 0.5 1.0 % 2.7v ? v dd ? 5.5v ( 2 ) 1.2 % 1.8v ( 2 ) v out tempco (see c.19 v out temperature coefficient ) ? v out / ? t 15 ppm/c code = mid-scale (7fh, 1ffh or 7ffh) v ref pin input voltage range v ref v ss v dd v1 . 8 v ? v dd ? 5.5v ( 1 ) note 1 this parameter is ensured by design. note 2 this parameter is ensured by characterization. note 7 resistance is defined as the resistance between the v ref pin (mode vrxb:vrxa = 10 ) to v ss pin. for dual-channel devices (mcp47febx2), this is the effective resistance of the each resistor ladder. the resistance measurement is of the two resistor ladders measured in parallel. note 12 variation of one output voltage to mean output voltage. downloaded from: http:///
? 2015 microchip technology inc. ds20005375a-page 9 mcp47febxx dc characteristics (continued) dc characteristics standard operating conditions (unless otherwise specified) operating temperature C40c ? t a ? +125c (extended) all parameters apply across the specified operating ranges unless noted. v dd = +2.7v to 5.5v, v ref = +2.048v to v dd , v ss = 0v, gx = 0 , r l = 5 k ? from v out to gnd, c l = 100 pf. typical specifications represent values for v dd = 5.5v, t a = +25c. parameters sym. min. typ. max. units conditions zero-scale error (see c.5 zero-scale error (ezs) ) (code = 000h) e zs 0.75 lsb 8-bit vrxb:vrxa = 11 , gx = 0 , v ref = v dd , no load see section 2.0 typical performance curves ( 2 ) lsb vrxb:vrxa = 00 , gx = 0 , v dd = 5.5v, no load see section 2.0 typical performance curves ( 2 ) lsb v dd = 1.8v, v ref = 1.0v vrxb:vrxa = 10 , gx = 0 . no load see section 2.0 typical performance curves ( 2 ) lsb v dd = 1.8v, v ref = 1.0v vrxb:vrxa = 11 , gx = 0 . no load see section 2.0 typical performance curves ( 2 ) lsb vrxb:vrxa = 01 , gx = 0 , no load 3 lsb 10-bit vrxb:vrxa = 11 , gx = 0 , v ref = v dd , no load see section 2.0 typical performance curves ( 2 ) lsb vrxb:vrxa = 00 , gx = 0 , v dd = 5.5v, no load see section 2.0 typical performance curves ( 2 ) lsb v dd = 1.8v, v ref = 1.0v vrxb:vrxa = 10 , gx = 0 . no load see section 2.0 typical performance curves ( 2 ) lsb v dd = 1.8v, v ref = 1.0v vrxb:vrxa = 11 , gx = 0 . no load see section 2.0 typical performance curves ( 2 ) lsb vrxb:vrxa = 01 , gx = 0 , no load 12 lsb 12-bit vrxb:vrxa = 11 , gx = 0 , v ref = v dd , no load see section 2.0 typical performance curves ( 2 ) lsb vrxb:vrxa = 00 , gx = 0 , v dd = 5.5v, no load see section 2.0 typical performance curves ( 2 ) lsb v dd = 1.8v, v ref = 1.0v vrxb:vrxa = 10 , gx = 0 . no load see section 2.0 typical performance curves ( 2 ) lsb v dd = 1.8v, v ref = 1.0v vrxb:vrxa = 11 , gx = 0 . no load see section 2.0 typical performance curves ( 2 ) lsb vrxb:vrxa = 01 , gx = 0 , no load offset error (see c.7 offset error (eos) ) e os -15 1.5 +15 mv vrxb:vrxa = 00 , gx = 0 , no load offset voltage temperature coefficient v ostc 1 0 v / c note 2 this parameter is ensured by characterization. downloaded from: http:///
mcp47febxx ds20005375a-page 10 ? 2015 microchip technology inc. dc characteristics (continued) dc characteristics standard operating conditions (unless otherwise specified) operating temperature C40c ? t a ? +125c (extended) all parameters apply across the specified operating ranges unless noted. v dd = +2.7v to 5.5v, v ref = +2.048v to v dd , v ss = 0v, gx = 0 , r l = 5 k ? from v out to gnd, c l = 100 pf. typical specifications represent values for v dd = 5.5v, t a = +25c. parameters sym. min. typ. max. units conditions full-scale error (see c.4 full-scale error (efs) ) e fs 4.5 lsb 8-bit code = ffh, vrxb:vrxa = 11 , gx = 0 , v ref = 2.048v, no load see section 2.0 typical performance curves ( 2 ) lsb code = ffh, vrxb:vrxa = 10 , gx = 0 , v ref = 2.048v, no load see section 2.0 typical performance curves ( 2 ) lsb code = ffh, vrxb:vrxa = 01 , gx = 0 , v ref = 2.048v, no load see section 2.0 typical performance curves ( 2 ) lsb code = ffh, vrxb:vrxa = 00 , no load 18 lsb 10-bit code = 3ffh, vrxb:vrxa = 11 , gx = 0 , v ref = 2.048v, no load see section 2.0 typical performance curves ( 2 ) lsb code = 3ffh, vrxb:vrxa = 10 , gx = 0 , v ref = 2.048v, no load see section 2.0 typical performance curves ( 2 ) lsb code = 3ffh, vrxb:vrxa = 01 , gx = 0 , v ref = 2.048v, no load see section 2.0 typical performance curves ( 2 ) lsb code = 3ffh, vrxb:vrxa = 00 , no load 70 lsb 12-bit code = fffh, vrxb:vrxa = 11 , gx = 0 , v ref = 2.048v, no load see section 2.0 typical performance curves ( 2 ) lsb code = fffh, vrxb:vrxa = 10 , gx = 0 , v ref = 2.048v, no load see section 2.0 typical performance curves ( 2 ) lsb code = fffh, vrxb:vrxa = 01 , gx = 0 , v ref = 2.048v, no load see section 2.0 typical performance curves ( 2 ) lsb code = fffh, vrxb:vrxa = 00 , no load note 2 this parameter is ensured by characterization. downloaded from: http:///
? 2015 microchip technology inc. ds20005375a-page 11 mcp47febxx dc characteristics (continued) dc characteristics standard operating conditions (unless otherwise specified) operating temperature C40c ? t a ? +125c (extended) all parameters apply across the specified operating ranges unless noted. v dd = +2.7v to 5.5v, v ref = +2.048v to v dd , v ss = 0v, gx = 0 , r l = 5 k ? from v out to gnd, c l = 100 pf. typical specifications represent values for v dd = 5.5v, t a = +25c. parameters sym. min. typ. max. units conditions gain error (see c.9 gain error (eg) ) ( 9 ) e g -1.0 0.1 +1.0 % of fsr 8-bit code = 250, no load vrxb:vrxa = 00 , gx = 0 -1.0 0.1 +1.0 % of fsr 10-bit code = 1000, no load vrxb:vrxa = 00 , gx = 0 -1.0 0.1 +1.0 % of fsr 12-bit code = 4000, no load vrxb:vrxa = 00 , gx = 0 gain-error drift (see c.10 gain-error drift (egd) ) ? g/c -3 ppm/c total unadjusted error (see c.6 total unadjusted error (et) ) ( 2 ) e t -2.5 +0.5 lsb 8-bit vrxb:vrxa = 00 . no load. see section 2.0 typical performance curves lsb v dd = 1.8v, vrxb:vrxa = 11 , gx = 0 , v ref = 1.0v, no load. -10.0 +2.0 lsb 10-bit vrxb:vrxa = 00 . no load. see section 2.0 typical performance curves lsb v dd = 1.8v, vrxb:vrxa = 11 , gx = 0 , v ref = 1.0v, no load. -40.0 +8.0 lsb 12-bit vrxb:vrxa = 00 . no load. see section 2.0 typical performance curves lsb v dd = 1.8v, vrxb:vrxa = 11 , gx = 0 , v ref = 1.0v, no load. note 2 this parameter is ensured by characterization. note 9 this gain error does not include offset error. downloaded from: http:///
mcp47febxx ds20005375a-page 12 ? 2015 microchip technology inc. dc characteristics (continued) dc characteristics standard operating conditions (unless otherwise specified) operating temperature C40c ? t a ? +125c (extended) all parameters apply across the specified operating ranges unless noted. v dd = +2.7v to 5.5v, v ref = +2.048v to v dd , v ss = 0v, gx = 0 , r l = 5 k ? from v out to gnd, c l = 100 pf. typical specifications represent values for v dd = 5.5v, t a = +25c. parameters sym. min. typ. max. units conditions integral nonlinearity (see c.11 integral nonlinearity (inl) ) ( 8 , 11 ) inl -0.5 0.1 +0.5 lsb 8-bit vrxb:vrxa = 10 (codes: 6 to 250), v dd = v ref = 5.5v. see section 2.0 typical performance curves ( 2 ) lsb vrxb:vrxa = 00 , 01 , 11 . see section 2.0 typical performance curves ( 2 ) lsb vrxb:vrxa = 01 , v dd = 5.5v, gx = 1 . see section 2.0 typical performance curves ( 2 ) lsb vrxb:vrxa = 10 , 11 , v ref = 1.0v, gx = 1 . see section 2.0 typical performance curves ( 2 ) lsb v dd = 1.8v, v ref = 1.0v -1.5 0.4 +1.5 lsb 10-bit vrxb:vrxa = 10 (codes: 25 to 1000), v dd = v ref = 5.5v. see section 2.0 typical performance curves ( 2 ) lsb vrxb:vrxa = 00 , 01 , 11 . see section 2.0 typical performance curves ( 2 ) lsb vrxb:vrxa = 01 , v dd = 5.5v, gx = 1 . see section 2.0 typical performance curves ( 2 ) lsb vrxb:vrxa = 10 , 11 , v ref = 1.0v, gx = 1 . see section 2.0 typical performance curves ( 2 ) lsb v dd = 1.8v, v ref = 1.0v. -6 1.5 +6 lsb 12-bit vrxb:vrxa = 10 (codes: 100 to 4000), v dd = v ref = 5.5v. see section 2.0 typical performance curves ( 2 ) lsb vrxb:vrxa = 00 , 01 , 11 . see section 2.0 typical performance curves ( 2 ) lsb vrxb:vrxa = 01 , v dd = 5.5v, gx = 1 . see section 2.0 typical performance curves ( 2 ) lsb vrxb:vrxa = 10 , 11 , v ref = 1.0v, gx = 1 . see section 2.0 typical performance curves ( 2 ) lsb v dd = 1.8v, v ref = 1.0v. note 2 this parameter is ensured by characterization. note 8 inl and dnl are measured at v out with v rl = v dd (vrxb:vrxa = 00 ) . note 11 code range dependent on resolution: 8-bit, codes 6 to 250; 10-bit, codes 25 to 1000; 12-bit, 100 to 4000. downloaded from: http:///
? 2015 microchip technology inc. ds20005375a-page 13 mcp47febxx dc characteristics (continued) dc characteristics standard operating conditions (unless otherwise specified) operating temperature C40c ? t a ? +125c (extended) all parameters apply across the specified operating ranges unless noted. v dd = +2.7v to 5.5v, v ref = +2.048v to v dd , v ss = 0v, gx = 0 , r l = 5 k ? from v out to gnd, c l = 100 pf. typical specifications represent values for v dd = 5.5v, t a = +25c. parameters sym. min. typ. max. units conditions differential nonlinearity (see c.12 differential nonlinearity (dnl) ) ( 8 , 11 ) dnl -0.25 0.0125 +0.25 lsb 8-bit vrxb:vrxa = 10 (codes: 6 to 250), v dd = v ref = 5.5v. see section 2.0 typical performance curves ( 2 ) lsb char: vrxb:vrxa = 00 , 01 , 11 . see section 2.0 typical performance curves ( 2 ) lsb char: vrxb:vrxa = 01 , v dd = 5.5v, gx = 1 . see section 2.0 typical performance curves ( 2 ) lsb char: vrxb:vrxa = 10 , 11 , v ref = 1.0v, gx = 1 . see section 2.0 typical performance curves ( 2 ) lsb v dd = 1.8v -0.5 0.05 +0.5 lsb 10-bit vrxb:vrxa = 10 (codes: 25 to 1000), v dd = v ref = 5.5v. see section 2.0 typical performance curves ( 2 ) lsb char: vrxb:vrxa = 00 , 01 , 11 . see section 2.0 typical performance curves ( 2 ) lsb char: vrxb:vrxa = 01 , v dd = 5.5v, gx = 1 . see section 2.0 typical performance curves ( 2 ) lsb char: vrxb:vrxa = 10 , 11 , v ref = 1.0v, gx = 1 . see section 2.0 typical performance curves ( 2 ) lsb v dd = 1.8v -1.0 0.2 +1.0 lsb 12-bit vrxb:vrxa = 10 (codes: 100 to 4000), v dd = v ref = 5.5v. see section 2.0 typical performance curves ( 2 ) lsb char: vrxb:vrxa = 00 , 01 , 11 . see section 2.0 typical performance curves ( 2 ) lsb char: vrxb:vrxa = 01 , v dd = 5.5v, gx = 1 . see section 2.0 typical performance curves ( 2 ) lsb char: vrxb:vrxa = 10 , 11 , v ref = 1.0v, gx = 1 . see section 2.0 typical performance curves ( 2 ) lsb v dd = 1.8v note 2 this parameter is ensured by characterization. note 8 inl and dnl are measured at v out with v rl = v dd (vrxb:vrxa = 00 ) . note 11 code range dependent on resolution: 8-bit, codes 6 to 250; 10-bit, codes 25 to 1000; 12-bit, 100 to 4000. downloaded from: http:///
mcp47febxx ds20005375a-page 14 ? 2015 microchip technology inc. dc characteristics (continued) dc characteristics standard operating conditions (unless otherwise specified) operating temperature C40c ? t a ? +125c (extended) all parameters apply across the specified operating ranges unless noted. v dd = +2.7v to 5.5v, v ref = +2.048v to v dd , v ss = 0v, gx = 0 , r l = 5 k ? from v out to gnd, c l = 100 pf. typical specifications represent values for v dd = 5.5v, t a = +25c. parameters sym. min. typ. max. units conditions -3 db bandwidth (see c.16 -3 db bandwidth ) bw 86.5 khz v ref = 2.048v 0.1v, vrxb:vrxa = 10 , gx = 0 6 7 . 7 k h zv ref = 2.048v 0.1v, vrxb:vrxa = 10 , gx = 1 output amplifier minimum output voltage v out(min) 0.01 v 1.8v ? v dd ? 5.5v, output amplifiers minimum drive maximum output voltage v out(max) v dd C 0.04 v 1.8v ? v dd ? 5.5v, output amplifiers maximum drive phase margin pm 66 degree () c l = 400 pf, r l = ? slew rate ( 10 ) sr 0.44 v/s r l = 5 k ? short-circuit current i sc 3 9 14 ma dac code = full scale internal band gap band gap voltage v bg 1.18 1.22 1.26 v band gap voltage temperature coefficient v bgtc 1 5 p p m / c operating range (v dd ) 2.0 5.5 v v ref pin voltage stable 2.2 5.5 v v out output linear external reference (v ref ) input range ( 1 ) v ref v ss v dd C 0.04 v vrxb:vrxa = 11 (buffered mode) v ss v dd v vrxb:vrxa = 10 (unbuffered mode) input capacitance c ref 1 pf vrxb:vrxa = 10 (unbuffered mode) total harmonic distortion ( 1 ) thd -64 db v ref = 2.048v 0.1v, vrxb:vrxa = 10 , gx = 0 , frequency = 1 khz dynamic performance major code transition glitch (see c.14 major-code transition glitch ) 45 nv-s 1 lsb change around major carry (7ffh to 800h) digital feedthrough (see c.15 digital feed-through ) < 1 0 n v - s note 1 this parameter is ensured by design. note 10 within 1/2 lsb of final value when code changes from 1/4 to 3/4 of fsr. (example: 400h to c00h in 12-bit device). downloaded from: http:///
? 2015 microchip technology inc. ds20005375a-page 15 mcp47febxx dc characteristics (continued) dc characteristics standard operating conditions (unless otherwise specified) operating temperature C40c ? t a ? +125c (extended) all parameters apply across the specified operating ranges unless noted. v dd = +2.7v to 5.5v, v ref = +2.048v to v dd , v ss = 0v, gx = 0 , r l = 5 k ? from v out to gnd, c l = 100 pf. typical specifications represent values for v dd = 5.5v, t a = +25c. parameters sym. min. typ. max. units conditions digital inputs/outputs (lat0 /hvc) schmitt trigger high- input threshold v ih 0.45 v dd v 2 . 7 v ? v dd ? 5.5v (allows 2.7v digital v dd with 5v analog v dd ) 0.5 v dd v 1 . 8 v ? v dd ? 2.7v schmitt trigger low- input threshold v il 0 . 2 v dd v hysteresis of schmitt trigger inputs v hys 0 . 1 v dd v input leakage current i il -1 1 a v in = v dd and v in = v ss pin capacitance c in , c out 1 0 p f f c = 3.4 mhz digital interface (sda, scl) output low voltage v ol 0 . 4 v v dd ? 2.0v, i ol = 3 ma 0 . 2 v dd vv dd < 2.0v, i ol = 1 ma input high voltage (sda and scl pins) v ih 0.7 v dd v 1 . 8 v ? v dd ? 5.5v input low voltage (sda and scl pins) v il 0 . 3 v dd v 1.8v ? v dd ? 5.5v input leakage i li -1 1 a scl = sda = v ss or scl = sda = v dd pin capacitance c pin 1 0 p f f c = 3.4 mhz note 1 this parameter is ensured by design. downloaded from: http:///
mcp47febxx ds20005375a-page 16 ? 2015 microchip technology inc. dc characteristics (continued) dc characteristics standard operating conditions (unless otherwise specified) operating temperature C40c ? t a ? +125c (extended) all parameters apply across the specified operating ranges unless noted. v dd = +2.7v to 5.5v, v ref = +2.048v to v dd , v ss = 0v, gx = 0 , r l = 5 k ? from v out to gnd, c l = 100 pf. typical specifications represent values for v dd = 5.5v, t a = +25c. parameters sym. min. typ. max. units conditions ram value value range n 0h ffh hex 8-bit 0h 3ffh hex 10-bit 0h fffh hex 12-bit dac register por/bor value ns e e table 4-2 hex 8-bit see table 4-2 hex 10-bit see table 4-2 hex 12-bit pdcon initial factory setting see table 4-2 hex eeprom endurance en ee 1 mc y c l e s note 1 , note 2 data retention dr ee 200 years at +25c ( 1 , 2 ) eeprom range n 0h ffh hex 8-bit dacx register(s) 0h 3ffh hex 10-bit dacx register(s) 0h fffh hex 12-bit dacx register(s) initial factory setting n see table 4-2 eeprom programming write cycle time t wc 1 11 6m sv dd = +1.8v to 5.5v power requirements power supply sensitivity ( c.17 power-supply sensitivity (pss) ) pss 0.002 0.005 %/% 8-bit code = 7fh 0.002 0.005 %/% 10-bit code = 1ffh 0.002 0.005 %/% 12-bit code = 7ffh note 1 this parameter is ensured by design. note 2 this parameter is ensured by characterization. downloaded from: http:///
? 2015 microchip technology inc. ds20005375a-page 17 mcp47febxx dc notes: 1. this parameter is ensured by design. 2. this parameter is ensured by characterization. 3. por/bor voltage trip point is not slope dependent. hysteresis implemented with time delay. 4. supply current is independent of current through the resistor ladder in mode vrxb:vrxa = 10 . 5. the pdxb:pdxa = 01 , 10 , and 11 configurations should have the same current. 6. by design, this is worst-case current mode. 7. resistance is defined as the resistance between the v ref pin (mode vrxb:vrxa = 10 ) to v ss pin. for dual- channel devices (mcp47febx2), this is the effective resistance of the each resistor ladder. the resi stance measurement is of the two resistor ladders measured in parallel. 8. inl and dnl are measured at v out with v rl = v dd (vrxb:vrxa = 00 ). 9. this gain error does not include offset error. 10. within 1/2 lsb of final value when code changes from 1/4 to 3/4 of fsr. (example: 400h to c00h in 12-bit device). 11. code range dependent on resolution: 8-bit, codes 6 to 250; 10-bit, codes 25 to 1000; 12-bit, 100 to 4000. 12. variation of one output voltage to mean output voltage. downloaded from: http:///
mcp47febxx ds20005375a-page 18 ? 2015 microchip technology inc. 1.1 timing waveforms and requirements figure 1-1: v out settling time waveforms. table 1-1: wiper settling timing timing characteristics standard operating conditions (unless otherwise specified) operating temperature C40c ? t a ? +125c (extended) all parameters apply across the specified operating ranges unless noted. v dd = +1.8v to 5.5v, v ss = 0v, r l = 5 k ? from v out to gnd, c l = 100 pf. typical specifications represent values for v dd = 5.5v, t a = +25c. parameters sym. min. typ. max. units conditions v out settling time (1lsb error band, c l = 100 pf ) (see c.13 settling time ) t s 6 s 8-bit code = 3fh ? bfh; bfh ? 3fh ( 1 ) 6 s 10-bit code = 0ffh ? 2ffh; 2ffh ? 0ffh ( 1 ) 6 s 12-bit code = 3ffh ? bffh; bffh ? 3ffh ( 1 ) note 1 within 1/2 lsb of final value when code changes from 1/4 to 3/4 of fsr. (example: 400h to c00h in 12- bit device). v out 1 lsb old value new value downloaded from: http:///
? 2015 microchip technology inc. ds20005375a-page 19 mcp47febxx 1.2 i 2 c mode timing waveforms and requirements figure 1-2: power-on and brown-out reset waveforms. figure 1-3: i 2 c? power-down command timing. table 1-2: reset timing timing characteristics standard operating conditions (unless otherwise specified) operating temperature C40c ? t a ? +125c (extended) all parameters apply across the specified operating ranges unless noted. v dd = +1.8v to 5.5v, v ss = 0v, r l = 5 k ? from v out to gnd, c l = 100 pf. typical specifications represent values for v dd = 5.5v, t a = +25c. parameters sym. min. typ. max. units conditions power-on reset delay t pord 60 s monitor ack bit response to ensure device responds to command. brown-out reset delay t bord 4 5 sv dd transitions from v dd(min) ? > v por v out driven to v out disabled power-down output disable time delay t pdd 10.5 s pdxb:pdxa = 11 , 10 , or 01 -> 00 started from fall- ing edge of the scl at the end of the 8th clock cycle. volatile dac register = ffh, v out =10mv. v out not connected. power-down output enable time delay t pde 1 s pdxb:pdxa = 00 ? 11 , 10 , or 01 started from falling edge of the scl at the end of the 8th clock cycle. v out = v out - 10 mv. v out not connected. v dd sda t pord t bord v out scl v ih v ih v por (v bor ) v out at high z i 2 c? interface is operational sdascl ack stop start ack v out t pde t pdd downloaded from: http:///
mcp47febxx ds20005375a-page 20 ? 2015 microchip technology inc. figure 1-4: i 2 c? bus start/stop bits timing waveforms. figure 1-5: i 2 c? bus start/stop bits timing waveforms. 91 93 scl sda start condition stop condition 90 92 lat 94 ack/ack pulse 96 95 96 91 93 scl sda start condition stop condition 90 92 v ih 111 v il downloaded from: http:///
? 2015 microchip technology inc. ds20005375a-page 21 mcp47febxx table 1-3: i 2 c bus start/stop bits and lat requirements i 2 c? ac characteristics standard operating conditions (unless otherwise specified) operating temperature C40 ? c ? t a ? +125 ? c (extended) operating voltage range is described in dc characteristics param. no. symbol characteristic min. max. units conditions f scl standard mode 0 100 khz c b = 400 pf, 1.8v - 5.5v ( 2 ) fast mode 0 400 khz c b = 400 pf, 2.7v - 5.5v high-speed 1.7 0 1.7 mhz c b = 400 pf, 4.5v - 5.5v high-speed 3.4 0 3.4 mhz c b = 100 pf, 4.5v - 5.5v d102 c b bus capacitive loading 100 khz mode 400 pf 400 khz mode 400 pf 1.7 mhz mode 400 pf 3.4 mhz mode 100 pf 90 t su:sta start condition setup time (only relevant for repeated start condition) 100 khz mode 4700 ns note 2 400 khz mode 600 ns 1.7 mhz mode 160 ns 3.4 mhz mode 160 ns 91 t hd:sta start condition hold time (after this period the first clock pulse is generated) 100 khz mode 4000 ns note 2 400 khz mode 600 ns 1.7 mhz mode 160 ns 3.4 mhz mode 160 ns 92 t su:sto stop condition setup time 100 khz mode 4000 ns note 2 400 khz mode 600 ns 1.7 mhz mode 160 ns 3.4 mhz mode 160 ns 93 t hd:sto stop condition hold time 100 khz mode 4000 ns note 2 400 khz mode 600 ns 1.7 mhz mode 160 ns 3.4 mhz mode 160 ns 94 t latsu lat to scl (write data ack bit) setup time 10 ns write data delayed ( 3 ) 95 t lathd scl to lat (write data ack bit) hold time 250 ns write data delayed ( 3 ) 96 t lat lat high or low time 50 ns 97 t hvcsu hvc high to scl high (of start condition) - setup time 25 s high-voltage commands 98 t hvchd scl low (of stop condition) to hvc low - hold time 25 s high-voltage commands note 2 not tested. this parameter ensured by characterization. note 3 the transition of the lat signal between 10 ns before the rising edge (spec 94) and 250 ns after the rising edge (spec 95) of the scl signal is indeterminate whether the change in v out is delayed or not. downloaded from: http:///
mcp47febxx ds20005375a-page 22 ? 2015 microchip technology inc. figure 1-6: i 2 c? bus timing waveforms. table 1-4: i 2 c bus requirements (slave mode) i 2 c? ac characteristics standard operating conditions (unless otherwise specified) operating temperature C40 ? c ? t a ? +125 ? c (extended) operating voltage range is described in dc characteristics param. no. sym. characteristic min. max. units conditions 100 t high clock high time 100 khz mode 4000 ns 1.8v-5.5v ( 2 ) 400 khz mode 600 ns 2.7v-5.5v 1.7 mhz mode 120 ns 4.5v-5.5v 3.4 mhz mode 60 ns 4.5v-5.5v 101 t low clock low time 100 khz mode 4700 ns 1.8v-5.5v ( 2 ) 400 khz mode 1300 ns 2.7v-5.5v 1.7 mhz mode 320 ns 4.5v-5.5v 3.4 mhz mode 160 ns 4.5v-5.5v 102a ( 2 ) t rscl scl rise time 100 khz mode 1000 ns c b is specified to be from 10 to 400 pf (100 pf maximum for 3.4 mhz mode) 400 khz mode 20 + 0.1c b 300 ns 1.7 mhz mode 20 80 ns 1.7 mhz mode 20 160 ns after a repeated start condition or an acknowledge bit 3.4 mhz mode 10 40 ns 3.4 mhz mode 10 80 ns after a repeated start condition or an acknowledge bit 102b ( 2 ) t rsda sda rise time 100 khz mode 1000 ns cb is specified to be from 10 to 400 pf (100 pf maximum for 3.4 mhz mode) 400 khz mode 20 + 0.1c b 300 ns 1.7 mhz mode 20 160 ns 3.4 mhz mode 10 80 ns note 2 not tested. this parameter ensured by characterization. 90 91 92 100 101 103 106 107 109 109 110 102 scl sdain sda out downloaded from: http:///
? 2015 microchip technology inc. ds20005375a-page 23 mcp47febxx table 1-5: i 2 c bus requirements (slave mode) (continued) i 2 c? ac characteristics standard operating conditions (unless otherwise specified) operating temperature C40 ? c ? t a ? +125 ? c (extended) operating voltage range is described in dc characteristics param. no. sym. characteristic min. max. units conditions 103a ( 2 ) t fscl scl fall time 100 khz mode 300 ns c b is specified to be from 10 to 400 pf (100 pf maximum for 3.4 mhz mode) ( 4 ) 400 khz mode 20 + 0.1c b 300 ns 1.7 mhz mode 20 80 ns 3.4 mhz mode 10 40 ns 103b ( 2 ) t fsda sda fall time 100 khz mode 300 ns c b is specified to be from 10 to 400 pf (100 pf maximum for 3.4 mhz mode) ( 4 ) 400 khz mode 20 + 0.1c b 300 ns 1.7 mhz mode 20 160 ns 3.4 mhz mode 10 80 ns 106 t hd:dat data input hold time 100 khz mode 0 ns 1.8v-5.5v ( 2 , 5 ) 400 khz mode 0 ns 2.7v-5.5v ( 5 ) 1.7 mhz mode 0 ns 4.5v-5.5v ( 5 ) 3.4 mhz mode 0 ns 4.5v-5.5v ( 5 ) 107 t su:dat data input setup time 100 khz mode 250 ns note 2 , note 6 400 khz mode 100 ns note 6 1.7 mhz mode 10 ns 3.4 mhz mode 10 ns 109 t aa output valid from clock 100 khz mode 3450 ns note 2 , note 7 400 khz mode 900 ns note 7 1.7 mhz mode 150 ns c b = 100 pf ( 7 , 8 ) 3 1 0n s c b = 400 pf ( 2 , 7 ) 3.4 mhz mode 150 ns c b = 100 pf ( 7 ) 110 t buf bus free time 100 khz mode 4700 ns time the bus must be free before a new transmis- sion can start ( 2 ) 400 khz mode 1300 ns 1.7 mhz mode n.a. ns 3.4 mhz mode n.a. ns 111 t sp input filter spike suppression (sda and scl) 100 khz mode 50 ns nxp spec states n.a. ( 2 ) 400 khz mode 50 ns 1.7 mhz mode 10 ns spike suppression 3.4 mhz mode 10 ns spike suppression note 2 not tested. this parameter ensured by characterization. note 4 use cb in pf for the calculations. note 5 a master transmitter must provide a delay to ensure that difference between sda and scl fall times do not unintentionally create a start or stop condition. note 6 a fast-mode (400 khz) i 2 c-bus device can be used in a standard-mode (100 khz) i 2 c-bus system, but the requirement t su;dat ? 250 ns must then be met. this will automatically be the case if the device does not stretch the low period of the scl signal. if such a device does stretch the low period of the scl si gnal, it must output the next data bit to the sda line t r max.+t su;dat = 1000 + 250 = 1250 ns (according to the standard-mode i 2 c bus specification) before the scl line is released. note 7 as a transmitter, the device must provide this internal minimum delay time to bridge the undefined region (minimum 300 ns) of the falling edge of scl to avoid unintended generation of start or stop conditions. note 8 ensured by the t aa 3.4 mhz specification test. downloaded from: http:///
mcp47febxx ds20005375a-page 24 ? 2015 microchip technology inc. timing table notes: 1. within 1/2 lsb of final value when code changes from 1/4 to 3/4 of fsr. (example: 400h to c00h in 12- bit device). 2. not tested. this parameter ensured by characterization. 3. the transition of the lat signal between 10 ns before the rising edge (spec 94) and 250 ns after the rising edge (spec 95) of the scl signal is indeterminate whether the change in v out is delayed or not. 4. use cb in pf for the calculations. 5. a master transmitter must provide a delay to ensure that difference between sda and scl fall times do not unintentionally create a start or stop condition. 6. a fast-mode (400 khz) i 2 c-bus device can be used in a standard-mode (100 khz) i 2 c-bus system, but the requirement t su;dat ? 250 ns must then be met. this will automatically be the case if the device does not stretch the low period of the scl signal. if such a device does stretch the low period of the scl signal, it must output the next data bit to the sda line t r max.+t su;dat = 1000 + 250 = 1250 ns (according to the standard-mode i 2 c bus specification) before the scl line is released. 7. as a transmitter, the device must provide this internal minimum delay time to bridge the undefined region (mini- mum 300 ns) of the falling edge of scl to avoid unintended generation of start or stop conditions. 8. ensured by the t aa 3.4 mhz specification test. downloaded from: http:///
? 2015 microchip technology inc. ds20005375a-page 25 mcp47febxx temperature specifications electrical specifications: unless otherwise indicated, v dd = +2.7v to +5.5v, v ss = gnd. parameters symbol min. typical max. units conditions temperature ranges specified temperature range t a -40 +125 c operating temperature range t a -40 +125 c note 1 storage temperature range t a -65 +150 c thermal package resistances thermal resistance, 8l-tssop ? ja 1 3 9 c / w note 1: the mcp47febxx devices operate over this extended temperature range, but with reduced performance. operation in this range must not cause t j to exceed the maximum junction temperature of +150c. downloaded from: http:///
mcp47febxx ds20005375a-page 26 ? 2015 microchip technology inc. notes: downloaded from: http:///
? 2015 microchip technology inc. ds20005375a-page 27 mcp47febxx 2.0 typical performance curves note: the device performance curves are available in a separate document. this is done to keep the file size of this pdf document less than the 10 mb file attachment limit of many mail servers. the mcp47fxbxx performance curves document is literature number ds20005378, and can be found on the microchip website. look at the mcp47febxx product page under documentation and software, in the data sheets category. downloaded from: http:///
mcp47febxx ds20005375a-page 28 ? 2015 microchip technology inc. notes: downloaded from: http:///
? 2015 microchip technology inc. ds20005375a-page 29 mcp47febxx 3.0 pin descriptions overviews of the pin functions are provided in sections 3.1 positive power supply input (v dd ) through section 3.8 i 2 c - serial data pin (sda) . the descriptions of the pins for the single-dac output device are listed in tab l e 3 - 1 , and descriptions for the dual-dac output device are listed in tab l e 3 - 2 . table 3-1: mcp47febx1 (singl e-dac) pinout description pin standard function tssop-8l symbol i/o buffer type 1v dd p supply voltage pin 2v ref0 a analog voltage reference input pin 3v out0 a analog buffered analog voltage output pin 4 nc not internally connected 5v ss p ground reference pin for all circuitries on the device 6 lat0/hvc i hv st dac register latch/high-voltage command pin. latch pin allows the value in the serial shift register to transfer to the volatile dac register. high-voltage command allows user configuration bits to be written. 7s c l is t i 2 c? serial clock pin 8 sda i/o st i 2 c serial data pin legend: a = analog st = schmitt trigger i = input o = output i/o = input/output p = power table 3-2: mcp47febx2 (dual -dac) pinout description pin standard function tssop-8 symbol i/o buffer type 1v dd p supply voltage pin 2v ref a analog voltage reference input pin (for dac0 or dac0 and dac1) 3v out0 a analog buffered analog voltage output 0 pin (dac0 output) 4v out1 a analog buffered analog voltage output 1 pin (dac1 output) 5v ss p ground reference pin for all circuitries on the device 6 lat/hvc i hv st dac register latch/high-voltage command pin. latch pin allows the value in the serial shift register to transfer to the volatile dac register(s) (for dac0 or dac0 and dac1). high-voltage command allows user configuration bits to be written. 7s c l is t i 2 c? serial clock pin 8 sda i/o st i 2 c serial data pin legend: a = analog st = schmitt trigger i = input o = output i/o = input/output p = power downloaded from: http:///
mcp47febxx ds20005375a-page 30 ? 2015 microchip technology inc. 3.1 positive power supply input (v dd ) v dd is the positive supply voltage input pin. the input supply voltage is relative to v ss . the power supply at the v dd pin should be as clean as possible for a good dac performance. it is recommended to use an appropriate bypass capacitor of about 0.1 f (ceramic) to ground. an additional 10 f capacitor (tantalum) in parallel is also recommended to further attenuate noise present in application boards. 3.2 voltage reference pin (v ref ) the v ref pin is either an input or an output. when the dacs voltage reference is configured as the v ref pin, the pin is an input. when the dacs voltage reference is configured as the internal band gap, the pin is an output. when the dacs voltage reference is configured as the v ref pin, there are two options for this voltage input: v ref pin voltage buffered or unbuffered. the buffered option is offered in cases where the external reference voltage does not have sufficient current capability to not drop its voltage when connected to the internal resistor ladder circuit. when the dacs voltage reference is configured as the device v dd , the v ref pin is disconnected from the internal circuit. when the dacs voltage reference is configured as the internal band gap, the v ref pins drive capability is minimal, so the output signal should be buffered. see section 5.2 voltage reference selection and register 4-2 for more details on the configuration bits. 3.3 analog output voltage pin (v out ) v out is the dac analog voltage output pin. the dac output has an output amplifier. the dac output range is dependent on the selection of the voltage reference source (and potential output gain selection). these are: device v dd - the full-scale range of the dac output is from v ss to approximately v dd . v ref pin - the full-scale range of the dac output is from v ss to g ? v rl , where g is the gain selection option (1x or 2x). internal band gap - the full-scale range of the dac output is from v ss to g ? (2 ? v bg ), where g is the gain selection option (1x or 2x). in normal mode, the dc impedance of the output pin is about 1 ? . in power-down mode, the output pin is internally connected to a known pull-down resistor of 1k ? , 100 k ? , or open. the power-down selection bits settings are shown register 4-3 ( ta b l e 5 - 5 ). 3.4 no connect (nc) the nc pin is not connected to the device. 3.5 ground (v ss ) the v ss pin is the device ground reference. the user must connect the v ss pin to a ground plane through a low-impedance connection. if an analog ground path is available in the application pcb (printed circuit board), it is highly recommended that the v ss pin be tied to the analog ground path or isolated within an analog ground plane of the circuit board. 3.6 latch pin (lat)/high-voltage command (hvc) the lat pin is used to force the transfer of the dac registers shift register to the dac output register. this allows dac outputs to be updated at the same time. the update of the vrxb:vrxa, pdxb:pdxa, gx bits are also controlled by the lat pin state. the hvc pin allows the devices nonvolatile user con- figuration bits to be programmed when the hvc pin is greater than the v ihh entry voltage. 3.7 i 2 c - serial clock pin (scl) the scl pin is the serial clock pin of the i 2 c interface. the mcp47febxxs i 2 c interface only acts as a slave and the scl pin accepts only external serial clocks. the input data from the master device is shifted into the sda pin on the rising edges of the scl clock and output from the device occurs at the falling edges of the scl clock. the scl pin is an open-drain n-channel driver. therefore, it needs an external pull-up resistor from the v dd line to the scl pin. refer to section 6.0 i 2 c serial interface module for more details of i 2 c serial interface communication. 3.8 i 2 c - serial data pin (sda) the sda pin is the serial data pin of the i 2 c interface. the sda pin is used to write or read the dac registers and configuration bits. the sda pin is an open-drain n-channel driver. therefore, it needs an external pull-up resistor from the v dd line to the sda pin. except for start and stop conditions, the data on the sda pin must be stable during the high period of the clock. the high or low state of the sda pin can only change when the clock signal on the scl pin is low. refer to section 6.0 i 2 c serial interface module for more details of i 2 c serial interface communication. downloaded from: http:///
? 2015 microchip technology inc. ds20005375a-page 31 mcp47febxx 4.0 general description the mcp47febx1 (mcp47feb01, mcp47feb11, and mcp47feb21) devices are single-channel voltage output devices. mcp47febx2 (mcp47feb02, mcp47feb12, and mcp47feb22) devices are dual- channel voltage output devices. these devices are offered with 8-bit (mcp47feb0x), 10-bit (mcp47feb1x) and 12-bit (mcp47feb2x) resolution and include nonvolatile memory (eeprom), an i 2 c serial interface and a write latch (lat) pin to control the update of the written dac value to the dac output pin. the devices use a resistor ladder architecture. the resistor ladder dac is driven from a software- selectable voltage reference source. the source can be either the devices internal v dd , an external v ref pin voltage (buffered or unbuffered) or an internal band gap voltage source. the dac output is buffered with a low power and precision output amplifier (op amp). this output amplifier provides a rail-to-rail output with low offset voltage and low noise. the gain (1x or 2x) of the output buffer is software configurable. this device also has user-programmable nonvolatile memory (eeprom), which allows the user to save the desired por/bor value of the dac register and device configuration bits. high voltage lock bits can be used to ensure that the devices output settings are not accidentally modified. the devices operates from a single supply voltage. this voltage is specified from 2.7v to 5.5v for full specified operation, and from 1.8v to 5.5v for digital operation. the device operates between 1.8v and 2.7v, but some device parameters are not specified. the main functional blocks are: power-on reset/brown-out reset (por/bor) device memory resistor ladder output buffer/v out operation internal band gap (voltage reference) i 2 c serial interface module 4.1 power-on reset/brown-out reset (por/bor) the internal power-on reset (por)/brown-out reset (bor) circuit monitors the power supply voltage (v dd ) during operation. this circuit ensures correct device start-up at system power-up and power-down events. the devices ram retention voltage (v ram ) is lower than the por/bor voltage trip point (v por /v bor ). the maximum v por /v bor voltage is less than 1.8v. por occurs as the voltage is rising (typically from 0v), while bor occurs as the voltage is falling (typically from v dd(min) or higher). the por and bor trip points are at the same voltage, and the condition is determined by whether the v dd voltage is rising or falling (see figure 4-1 ). what occurs is different depending on if the reset is a por or bor reset. when v por /v bor mcp47febxx ds20005375a-page 32 ? 2015 microchip technology inc. 4.1.1 power-on reset the power-on reset is the case where the device v dd is having power applied to it from the v ss voltage level. as the device powers-up, the v out pin will float to an unknown value. when the devices v dd is above the transistor threshold voltage of the device, the output will start being pulled low. after the v dd is above the por/bor trip point (v bor /v por ), the resistor networks wiper will be loaded with the por value (mid-scale). the volatile memory determines the analog output (v out ) pin voltage. after the device is powered-up, the user can update the device memory. when the rising v dd voltage crosses the v por trip point, the following occurs: nonvolatile dac register value latched into volatile dac register nonvolatile configuration bit values latched into volatile configuration bits por status bit is set ( 1 ) the reset delay timer (t pord ) starts; when the reset delay timer (t pord ) times out, the i 2 c serial interface is operational. during this delay time, the i 2 c interface will not accept commands. the device memory address pointer is forced to 00h. the analog output (v out ) state will be determined by the state of the volatile configuration bits and the dac register. this is called a power-on reset (event). figure 4-1 illustrates the conditions for power-up and power-down events under typical conditions. 4.1.2 brown-out reset the brown-out reset occurs when a device had power applied to it, and that power (voltage) drops below the specified range. when the falling v dd voltage crosses the v por trip point (bor event), the following occurs: serial interface is disabled eeprom writes are disabled device is forced into a power-down state (pdxb:pdxa = 11 ). analog circuitry is turned off. volatile dac register is forced to 000h volatile configuration bits vrxb:vrxa and gx are forced to 0 if the v dd voltage decreases below the v ram voltage, all volatile memory may become corrupted. as the voltage recovers above the v por /v bor voltage see section 4.1.1 power-on reset . serial commands not completed due to a brown-out condition may cause the memory location (volatile and nonvolatile) to become corrupted. figure 4-1 illustrates the conditions for power-up and power-down events under typical conditions. figure 4-1: power-on reset operation. v por t pord (20 s max.) v dd(min) normal operation bor reset, volatile dac register = 000h volatile vrxb:vrxa = 00 device in below v ram device in por state unknown state minimum operating voltage device in unknown state device in power down state volatile gx = 0 volatile pdxb:pdxa = 11 v bor volatile memory retains data value volatile memory becomes corrupted por starts reset delay timer. when timer times out, i 2 c? interface can operate (if v dd ? v dd(min) ) eeprom data latched into volatile configuration bits and dac register. por status bit is set ( 1 ) por reset forced active downloaded from: http:///
? 2015 microchip technology inc. ds20005375a-page 33 mcp47febxx 4.2 device memory user memory includes three types of memory: volatile register memory (ram) nonvolatile register memory device configuration memory each memory address is 16 bits wide. there are five nonvolatile user-control bits that do not reside in mem- ory mapped register space (see section 4.2.3 device configuration memory ). 4.2.1 volatile register memory (ram) there are up to six volatile memory locations: dac0 and dac1 output value registers vref select register power-down configuration register gain and status register wiperlock technology status register the volatile memory starts functioning when the device v dd is at (or above) the ram retention voltage (v ram ). the volatile memory will be loaded with the default device values when the v dd rises across the v por /v bor voltage trip point. 4.2.2 nonvolatile register memory this memory can be grouped into two uses of nonvol- atile memory. these are the dac output value and configuration registers: nonvolatile dac0 and dac1 output value regis- ters nonvolatile vref select register nonvolatile power down configuration register nonvolatile gain and i 2 c slave address the nonvolatile memory starts functioning below the devices v por /v bor trip point and is loaded into the corresponding volatile registers whenever the device rises above the por/bor voltage trip point. the device starts writing the eeprom memory location at the completion of the serial interface command. for the i 2 c interface, this is the acknowledge pulse of the eeprom write command. the nonvolatile dac registers enables stand-alone operation of the device (without microcontroller control) after being programmed to the desired value. note: when the nonvolatile memory is written, the corresponding volatile memory is not modified. table 4-1: memory map (x16) address function config bit ( 1 ) address function config bit ( 1 ) 00h volatile dac0 register cl0 10h nonvolatile dac0 register dl0 01h volatile dac1 register cl1 11h nonvolatile dac1 register dl1 02h reserved 12h reserved 03h reserved 13h reserved 04h reserved 14h reserved 05h reserved 15h reserved 06h reserved 16h reserved 07h reserved 17h reserved 08h v ref register 18h nonvolatile v ref register 09h power-down register 19h nonvolatile power-down register 0ah gain and status register 1ah nv gain and i 2 c? 7-bits slave address salck 0bh wiperlock technology status register 1bh reserved 0ch reserved 1ch reserved 0dh reserved 1dh reserved 0eh reserved 1eh reserved 0fh reserved 1fh reserved volatile memory address range nonvolatile memory address range note 1: device configuration memory bits requires a high-voltage enable or disable command (lat /lat0 = v ihh , or cs = v ihh ) to modify the bit value. downloaded from: http:///
mcp47febxx ds20005375a-page 34 ? 2015 microchip technology inc. 4.2.3 device configuration memory there are up to five nonvolatile user bits that are not directly mapped into the address space. these nonvolatile device configuration bits control the following functions: dac register and configuration wiperlock technology (2 bits per dac) i 2 c slave address write protect (lock) the status register shows the states of the device wiperlock technology configuration bits. the status register is described in register 4-6 . the operation of wiperlock technology is discussed in section 4.2.6 wiperlock technology while i 2 c slave address write protect is discussed in section 4.2.7 i 2 c slave address write protect . 4.2.4 unimplemented register bits read commands of a valid location will read unimple- mented bits as 0 . 4.2.5 unimplemented (reserved) locations normal (voltage) commands (read or write) to any unimplemented memory address (reserved) will result in a command error condition (nack). read commands of a reserved location will read bits as 1 . high-voltage commands (enable or disable) to any unimplemented configuration bits will result in a command error condition (nack). 4.2.5.1 default factory por memory state of nonvolatile memory (eeprom) table 4-2 shows the default factory por initialization of the device memory map for the 8-, 10- and 12-bit devices. note: the volatile memory locations will be deter- mined by the nonvolatile memory states (registers and device configuration bits). table 4-2: factory default por / bor values address function por/bor value address function por/bor value 8-bit 10-bit 12-bit 8-bit 10-bit 12-bit 00h volatile dac0 register 7fh 1ffh 7ffh 10h nonvolatile dac0 register 7fh 1ffh 7ffh 01h volatile dac1 register 7fh 1ffh 7ffh 11h nonvolatile dac1 register 7fh 1ffh 7ffh 02h reserved ( 2 ) ffh 3ffh fffh 12h reserved ( 2 ) ffh 3ffh fffh 03h reserved ( 2 ) ffh 3ffh fffh 13h reserved ( 2 ) ffh 3ffh fffh 04h reserved ( 2 ) ffh 3ffh fffh 14h reserved ( 2 ) ffh 3ffh fffh 05h reserved ( 2 ) ffh 3ffh fffh 15h reserved ( 2 ) ffh 3ffh fffh 06h reserved ( 2 ) ffh 3ffh fffh 16h reserved ( 2 ) ffh 3ffh fffh 07h reserved ( 2 ) ffh 3ffh fffh 17h reserved ( 2 ) ffh 3ffh fffh 08h v ref register 0000h 0000h 0000h 18h nonvolatile v ref register 0000h 0000h 0000h 09h power-down register 0000h 0000h 0000h 19h nonvolatile power-down register 0000h 0000h 0000h 0ah gain and status register 0080h 0080h 0080h 1ah nv gain and i 2 c? 7-bit slave address ( 1 ) 00 e0 h ( 1 ) 00 e0 h ( 1 ) 00 e0 h ( 1 ) 0bh wiperlock technology status register 0000h 0000h 0000h 1bh reserved ( 2 ) ffh 3ffh fffh 0ch reserved ( 2 ) ffh 3ffh fffh 1ch reserved ( 2 ) ffh 3ffh fffh 0dh reserved ( 2 ) ffh 3ffh fffh 1dh reserved ( 2 ) ffh 3ffh fffh 0eh reserved ( 2 ) ffh 3ffh fffh 1eh reserved ( 2 ) ffh 3ffh fffh 0fh reserved ( 2 ) ffh 3ffh fffh 1fh reserved ( 2 ) ffh 3ffh fffh volatile memory address range nonvolatile memory address range note 1: a0 i 2 c 7-bit slave address option is 110 0000 and the slave address lock (salck) bit is enabled ( 1 ). 2: reading a reserved memory location will result in the i 2 c command to not ack the command byte. the device data bits will output all 1 s. a start condition will reset the i 2 c interface. downloaded from: http:///
? 2015 microchip technology inc. ds20005375a-page 35 mcp47febxx 4.2.6 wiperlock technology the mcp47febxx devices wiperlock technology allows application-specific device settings (dac regis- ter and configuration) to be secured without requiring the use of an additional write-protect pin. there are two configuration bits (dlx:clx) for each dac (dac0 and dac1). dependent on the state of the dlx:clx configuration bits, wiperlock technology prevents the serial commands from the following actions on the dacx registers and bits: writing to the specified volatile dacx register memory location writing to the specified nonvolatile dacx register memory location writing to the specified volatile dacx configuration bits writing to the specified nonvolatile dacx configuration bits each pair of these configuration bits control one of four modes. these modes are shown in table 4-4 . the addresses for the configuration bits are shown in table 4-1 . to modify the configuration bits, the hvc pin must be forced to the v ihh state and then receive an enable or disable command on the desired pair of dac register addresses. please refer to the section 7.5 enable configura- tion bit (high-voltage) and section 7.6 disable configuration bit (high-voltage) commands for operation. 4.2.6.1 por/bor operation when wiperlock technology enabled the wiperlock technology state is not affected by a por/bor event. a por/bor event will load the volatile dac0 (dac1) register values with the nonvolatile dac0 (dac1) register values. 4.2.7 i 2 c slave address write protect the mcp47febxx devices i 2 c slave address is stored in the eeprom memory. this allows the address to be modified to the applications requirement. to ensure that the i 2 c slave address is not unintentionally modified, the memory has a high voltage write protect bit. this configurations bit is shown in tab l e 4 - 3 . note: to modify the cl0 bit, the enable or dis- able command specifies address 00h, while to modify the dl0 bit, the enable or disable command specifies address 10h. note: during device communication, if the device address/command combination is invalid or an unimplemented address is specified, then the mcp47febxx will nack that byte. to reset the i 2 c state machine, the i 2 c communication must detect a start bit. note: to modify the salck bit, the enable or disable command specifies address 1ah. table 4-3: salck functional description salck operation 1 the nonvolatile i 2 c? slave address bits (add6:add0) are locked 0 the nonvolatile i 2 c slave address bits (add6:add0) are unlocked table 4-4: wiperlock technology conf iguration bits funct ional description dlx:clx ( 2 ) register / bits comments dacx dacx configuration ( 1 ) volatile nonvolatile volatile nonvolatile 11 locked locked locked locked all dacx registers are locked 10 locked locked unlocked locked all dacx registers are locked except volatile dacx configuration registers. this allows operation of power-down modes 01 unlocked locked unlocked locked volatile dacx registers unlocked, nonvolatile dacx registers locked 00 unlocked unlocked unlocked unlocked all dacx registers are unlocked note 1: dac configuration bits include voltage reference control bits (vrxb:vrxa), power-down control bits (pdxb:pdxa), and output gain bits (gx). 2: the state of these configuration bits (dlx:clx) are reflected in wlxb:wlxa bits as shown in register 4-6 . downloaded from: http:///
mcp47febxx ds20005375a-page 36 ? 2015 microchip technology inc. 4.2.8 device registers register 4-1 shows the format of the dac output value registers for both the volatile memory locations and the nonvolatile memory locations. these registers will be either 8 bits, 10 bits, or 12 bits wide. the values are right justified. register 4-1: dac0 and dac1 registers (vol atile and nonvolatile) u-0 u-0 u-0 u-0 r/w-0r/w-0r/w-0r/w-0r/w-0r/w-0r/w-0r/w-0r/w-0r/w-0r/w-0r/w -0 12-bit d11 d10 d09 d08 d07 d06 d05 d04 d03 d02 d01 d00 10-bit ( 1 ) ( 1 ) d09 d08 d07 d06 d05 d04 d03 d02 d01 d00 8-bit ( 1 ) ( 1 ) ( 1 ) ( 1 ) d07 d06 d05 d04 d03 d02 d01 d00 bit 15 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unkno wn = 12-bit device = 10-bit device = 8-bit device 12-bit 10-bit 8-bit bit 15-12 bit 15-10 bit 15-8 unimplemented: read as 0 bit 11-0 d11-d00: dac output value - 12-bit devices fffh = full-scale output value 7ffh = mid-scale output value 000h =zero-scale output value bit 9-0 d09-d00: dac output value - 10-bit devices 3ffh = full-scale output value 1ffh = mid-scale output value 000h =zero-scale output value b i t 7 - 0 d07-d00: dac output value - 8-bit devices ffh = full-scale output value 7fh = mid-scale output value 000h =zero-scale output value note 1: unimplemented bit, read as 0 . downloaded from: http:///
? 2015 microchip technology inc. ds20005375a-page 37 mcp47febxx register 4-2 shows the format of the voltage refer- ence control register. each dac has two bits to con- trol the source of the voltage reference of the dac. this register is for both the volatile memory locations and the nonvolatile memory locations. the width of this reg- ister is 2 times the number of dacs for the device. register 4-2: voltage reference (v ref) control register (volatile and nonvolatile) (addresses 08h and 18h) u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 single ( 1 ) ( 1 ) vr0b vr0a dual vr1b vr1a vr0b vr0a bit 15 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unkno wn = single-channel device = dual-channel device single dual bit 15-2 bit 15-4 unimplemented: read as 0 bit 1-0 bit 3-0 vrxb-vrxa: dac voltage reference control bits 11 =v ref pin (buffered); v ref buffer enabled. 10 =v ref pin (unbuffered); v ref buffer disabled. 01 = internal band gap (1.22v typical); v ref buffer enabled. v ref voltage driven when powered-down. 00 =v dd (unbuffered); v ref buffer disabled. use this state with power-down bits for lowest current. note 1: unimplemented bit, read as 0 . downloaded from: http:///
mcp47febxx ds20005375a-page 38 ? 2015 microchip technology inc. register 4-3 shows the format of the power-down control register. each dac has two bits to control the power-down state of the dac. this register is for both the volatile memory locations and the nonvolatile mem- ory locations. the width of this register is 2 times the number of dacs for the device. register 4-3: power-down control register (vol atile and nonvolatile) (addresses 09h, 19h) u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 single ( 1 ) ( 1 ) pb0b pb0a dual pb1b pb1a pb0b pb0a bit 15 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unkno wn = single-channel device = dual-channel device single dual bit 15-2 bit 15-4 unimplemented: read as 0 bit 1-0 bit 3-0 pbxb-pbxa: dac power-down control bits ( 2 ) 11 = powered down - v out is open circuit. 10 = powered down - v out is loaded with a 100 k ? resistor to ground. 01 = powered down - v out is loaded with a 1 k ? resistor to ground. 00 = normal operation (not powered-down). note 1: unimplemented bit, read as 0 . 2: see table 5-5 and figure 5-10 for more details. downloaded from: http:///
? 2015 microchip technology inc. ds20005375a-page 39 mcp47febxx register 4-4 shows the format of the gain control and system status register. each dac has one bit to con- trol the gain of the dac and three status bits. this reg- ister is for both the volatile memory locations and the nonvolatile memory locations. register 4-4: gain control and system status register (volatile) (address 0ah ) u-0 u-0 u-0 u-0 u-0 u-0 r/w-0 r/w-0 r/c-1 r/w-0 u-0 u-0 u-0 u-0 u-0 u-0 single ( 1 ) g0 por eewa dual g1 g0 por eewa bit 15 bit 0 legend: r = readable bit w = writable bit c = clear-able bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unkno wn = single-channel device = dual-channel device single dual bit 15-9 bit 15-10 unimplemented: read as 0 bit 9 g1: dac1 output driver gain control bits ( dual-channel device only ) 1 = 2x gain. not applicable when v dd is used as v rl . 0 =1x gain. bit 8 bit 8 g0: dac0 output driver gain control bits 1 = 2x gain. not applicable when v dd is used as v rl . 0 =1x gain. bit 7 bit 7 por: power-on reset (brown-out reset) status bit this bit indicates if a power-on reset (por) or brown-out reset (bor) event has occurred since the last read command of this register. reading this register clears the state of the por status bit. 1 = a por (bor) event occurred since the last read of this register. reading this register clears this bit. 0 = a por (bor) event has not occurred since the last read of this register. bit 6 bit 6 eewa: eeprom write active status bit this bit indicates if the eeprom write cycle is occurring 1 = an eeprom write cycle is currently occurring. only serial commands to the volatile mem- ory are allowed. 0 = an eeprom write cycle is not currently occurring. bit 5-0 bit 5-0 unimplemented: read as 0 note 1: unimplemented bit, read as 0 . downloaded from: http:///
mcp47febxx ds20005375a-page 40 ? 2015 microchip technology inc. register 4-5 shows the format of the nonvolatile gain control and slave address register. each dac has one bit to control the gain of the dac. i 2 c devices also have eight bits that are the i 2 c slave address and the status of the i 2 c address lock bit. register 4-5: gain control and slave address register (nonvolatile) (address 1ah) u-0 u-0 u-0 u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 single ( 1 ) g0 adlck eewa add6 add5 add4 add3 add2 add1 add0 dual g1 g0 adlck eewa add6 add5 add4 add3 add2 add1 add0 bit 15 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unkno wn = single-channel device = dual-channel device single dual bit 15-9 bit 15-10 unimplemented: read as 0 bit 9 g1: dac1 output driver gain control bits ( dual-channel device only ) ( 2 ) 1 = 2x gain. not applicable when v dd is used as v rl . 0 =1x gain. bit 8 bit 8 g0: dac0 output driver gain control bits ( 3 ) 1 = 2x gain. not applicable when v dd is used as v rl . 0 =1x gain. bit 7 bit 7 adlck: i 2 c address lock status bit (read-only bit; reflects the state of the salck configura- tion bit). 1 = i 2 c slave address is locked (requires hv command to disable, so i 2 c address can be changed) 0 = i 2 c slave address is not lock, the nonvolatile i 2 c slave address can be changed. bit 6-0 bit 6-0 add6-add0: i 2 c 7-bit slave address bits. note 1: unimplemented bit, read as 0 . 2: if vr1b:vr1a = 00 ; the device uses a gain of 1 only, regardless of the state of this bit (g1). 3: if vr0b:vr0a = 00 ; the device uses a gain of 1 only, regardless of the state of this bit (g0). downloaded from: http:///
? 2015 microchip technology inc. ds20005375a-page 41 mcp47febxx register 4-6 shows the format of the dac wiperlock technology status register. the width of this register is 2 times the number of dacs for the device. register 4-6: dac wiperlock technology status register (v olatile) (address 0bh) u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 r-0 ( 2 ) r-0 ( 2 ) r-0 ( 2 ) r-0 ( 2 ) single ( 1 ) ( 1 ) wl0b wl0a dual wl1b wl1a wl0b wl0a bit 15 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unkno wn = single-channel device = dual-channel device single dual bit 15-2 bit 15-4 unimplemented: read as 0 bit 1-0 bit 3-0 wlxb-wlxa: wiperlock technology status bits: these bits reflect the state of the dlx:clx nonvolatile configuration bits 11 = dac wiper and dac configuration (volatile and nonvolatile registers) are locked (dlx = clx = enabled) 10 = dac wiper (volatile and nonvolatile) and dac configuration (nonvolatile registers) are locked (dlx = enabled; clx = disabled). 01 = dac wiper (nonvolatile) and dac configuration (nonvolatile registers) are locked (dlx = disabled; clx = enabled) 00 = dac wiper and dac configuration are unlocked (dlx = clx = disabled). note 1: unimplemented bit, read as 0 . 2: por value dependent on the programmed values of the dlx:clx configuration bits. the devices are shipped with a default dlx:clx configuration bit state of 0 . downloaded from: http:///
mcp47febxx ds20005375a-page 42 ? 2015 microchip technology inc. notes: downloaded from: http:///
? 2015 microchip technology inc. ds20005375a-page 43 mcp47febxx 5.0 dac circuitry the digital to analog converter circuitry converts a digital value into its analog representation. the description describes the functional operation of the device. the dac circuit uses a resistor ladder implementation. devices have up to two dacs. figure 5-1 shows the functional block diagram for the mcp47febxx dac circuitry. the functional blocks of the dac include: resistor ladder voltage reference selection output buffer/v out operation internal band gap (as a voltage reference) latch pin (lat) power-down operation figure 5-1: mcp47febxx dac module block diagram. r s(2) v ref + - dac output r s(1) r s(2 n - 1) r s(2 n - 2) r s(2 n - 3) r s(2 n ) + - v dd v rl gain (1x or 2x) v out 1 k ? 100 k ? pd1:pd0 v dd pd1:pd0 v dd pd1:pd0 and pd1:pd0 vref1:vref0 v w r rl (~140 k ? ) band gap (1.22v typical) v dd vref1:vref0 pd1:pd0 and bgen selection internal band gap voltage reference selection resistor ladder output buffer/v out operation power-down operation power-down operation power-down operation a (rl) b vref1:vref0 where: # resistors in resistor ladder = 256 ( mcp47feb0x ) 1024 ( mcp47feb1x ) 4096 ( mcp47feb2x ) v w dac register value # resistor in resistor ladder --------------------------------------------------------------------- -v rl ? = downloaded from: http:///
mcp47febxx ds20005375a-page 44 ? 2015 microchip technology inc. 5.1 resistor ladder the resistor ladder is a digital potentiometer with the b terminal internally grounded and the a terminal connected to the selected reference voltage (see figure 5-2 ). the volatile dac register controls the wiper position. the wiper voltage (v w ) is proportional to the dac register value divided by the number of resis- tor elements (r s ) in the ladder (256, 1024 or 4096) related to the v rl voltage. the output of the resistor network will drive the input of an output buffer. the resistor network is made up of these three parts: resistor ladder (string of r s elements) wiper switches dac register decode the resistor ladder (r rl ) has a typical impedance of approximately 140 k ? . this resistor ladder resistance (r rl ) may vary from device to device up to 20%. since this is a voltage divider configuration, the actual r rl resistance does not affect the output given a fixed voltage at v rl . equation 5-1 shows the calculation for the step resistance. if the unbuffered v ref pin is used as the v rl voltage source, this voltage source should have a low output impedance. when the dac is powered-down, the resistor ladder is disconnected from the selected reference voltage. figure 5-2: resistor ladder model block diagram. equation 5-1: r s calculation note: the maximum wiper position is 2 n C1, while the number of resistors in the resistor ladder is 2 n . this means that when the dac register is at full scale, there is one resistor element (r s ) between the wiper and the v rl voltage. r s(2 n ) r s(2 n - 1) r s(2 n - 2) r s(1) 2 n - 1 2 n - 2 10 r rl v rl v w dac register pd1:pd0 analog mux r w (1) r w (1) r w ( 1 ) r w ( 1 ) where: # resistors in r-ladder = 256 ( mcp47feb0x ) 1024 ( mcp47feb1x ) 4096 ( mcp47feb2x ) v w dac register value # resistor in resistor ladder --------------------------------------------------------------------- -v rl ? = note 1: the analog switch resistance (r w ) does not affect performance due to the voltage divider configuration. r s r rl 256 ?? ------------- = r s r rl 1024 ?? ---------------- = 8-bit device 10-bit device r s r rl 4096 ?? ---------------- = 12-bit device downloaded from: http:///
? 2015 microchip technology inc. ds20005375a-page 45 mcp47febxx 5.2 voltage reference selection the resistor ladder has up to four sources for the refer- ence voltage. two user control bits (vref1:vref0) are used to control the selection, with the selection con- nected to the v rl node (see figures 5-3 and 5-4 ). the four voltage source options for the resistor ladder are: 1. v dd pin voltage 2. internal voltage reference (v bg ) 3. v ref pin voltage unbuffered 4. v ref pin voltage internally buffered the selection of the voltage is specified with the volatile v ref1 :v ref0 configuration bits (see register 4-2 ). there are nonvolatile and volatile vref1:vref0 configuration bits. on a por/bor event, the state of the nonvolatile vref1:vref0 configuration bits is latched into the volatile vref1:vref0 configuration bits. when the user selects the v dd as reference, the v ref pin voltage is not connected to the resistor ladder. if the v ref pin is selected, then one needs to select between the buffered or unbuffered mode. 5.2.1 unbuffered mode the v ref pin voltage may be from v ss to v dd . 5.2.2 buffered mode the v ref pin voltage may be from 0.01v to v dd - 0.04v. the input buffer (amplifier) provides low offset voltage, low noise, and a very high input impedance, with only minor limitations on the input range and fre- quency response. figure 5-3: resistor ladder reference voltage selection block diagram. figure 5-4: reference voltage selection implementation block diagram. 5.2.3 bandgap mode if the internal band gap is selected, then the external v ref pin should not be driven and only use high-impedance loads. decoupling capacitors are recommended for optimal operation. the band gap output is buffered, but the internal switches limit the current that the output should source to the v ref pin. the resistor ladder buffer is used to drive the band gap voltage for the cases of multiple dac outputs. this ensures that the resistor ladders are always properly sourced when the band gap is selected. note 1: the voltage source should have a low output impedance. if the voltage source has a high output impedance, then the voltage on the v ref s pin would be lower than expected. the resistor ladder has a typical impedance of 140 k ? and a typi- cal capacitance of 29 pf. 2: if the v ref pin is tied to the v dd volt- age, v dd mode (vref1:vref0 = 00 ) is recommended. note 1: any variation or noises on the reference source can directly affect the dac output. the reference voltage needs to be as clean as possible for accurate dac performance. 2: if the v ref pin is tied to the v dd volt- age, v dd mode (vref1:vref0 = 00 ) is recommended. v rl v dd buffer reference vref1:vref0 selection v ref band gap v ref + - v dd v dd pd1:pd0 and vref1:vref0 band gap ( 1 ) (1.22v typical) v dd vref1:vref0 pd1:pd0 v rl note 1: the band gap voltage (v bg ) is 1.22v typical. the band gap output goes through the buffer with a 2x gain to create the v rl voltage. see section 5.4 internal band gap for addition information on the band gap circuit. vref1:vref0 and bgen downloaded from: http:///
mcp47febxx ds20005375a-page 46 ? 2015 microchip technology inc. 5.3 output buffer/v out operation the output driver buffers the wiper voltage (v w ) of the resistor ladder. the dac output is buffered with a low power and precision output amplifier (op amp). this amplifier provides a rail-to-rail output with low offset voltage and low noise. the amplifiers output can drive the resistive and high-capacitive loads without oscillation. the amplifier provides a maximum load current which is enough for most programmable voltage reference applications. refer to section 1.0 electrical characteristics for the specifications of the output amplifier. figure 5-5 shows a block diagram of the output driver circuit. the user can select the output gain of the output amplifier. gain options are: a) gain of 1, with either v dd or v ref pin used as reference voltage. b) gain of 2, only when v ref pin or internal band gap is used as reference voltage. the v ref pin voltage should be limited to v dd /2. power-down logic also controls the output buffer oper- ation (see section 5.6 power-down operation for additional information on power-down). in any of the three power-down modes, the op amp is powered- down and its output becomes a high impedance to the v out pin. table 5-1 shows the gain bit operation. when the reference voltage selection (v rl ) is the devices v dd voltage, the g bit is ignored and a gain of 1 is used. figure 5-5: output driver block diagram. 5.3.1 programmable gain the amplifiers gain is controlled by the gain (g) configuration bit (see register 4-5 ) and the v rl refer- ence selection. when the v rl reference selection is the devices v dd voltage, the g bit is ignored and a gain of 1 is used. the volatile g bit value can be modified by: por event bor event i 2 c write commands i 2 c general call reset command note: the load resistance must keep higher than 5k ? for the stable and expected analog output (to meet electrical specifications). + - gain ( 1 ) v out 1 k ? 100 k ? pd1:pd0 v dd pd1:pd0 v w note 1: gain options are 1x and 2x. table 5-1: output driver gain gain bit gain comment 0 1 1 2 limits v ref pin voltages relative to device v dd voltage. downloaded from: http:///
? 2015 microchip technology inc. ds20005375a-page 47 mcp47febxx 5.3.2 output voltage the volatile dac register values along with the devices configuration bits control the analog v out volt- age. the volatile dac registers value is unsigned binary. the formula for the output voltage is given in equation 5-2 . table 5-3 shows examples of volatile dac register values and the corresponding theoretical v out voltage for the mcp47febxx devices. equation 5-2: calculating output voltage (v out ) the following events update the dac register value and therefore the analog voltage output (v out ): power-on reset brown-out reset i 2 c write command, falling edge of the acknowl- edge pulse of the last write command byte. i 2 c general call reset command, output is updated with por data (eeprom). then the v out voltage will start driving to the new value after the event has occurred. 5.3.3 step voltage (v s ) the step voltage is dependent on the device resolution and the calculated output voltage range. one lsb is defined as the ideal voltage difference between two successive codes. the step voltage can easily be cal- culated by using equation 5-3 (dac register value is equal to 1). theoretical step voltages are shown in table 5-2 for several v ref voltages. equation 5-3: v s calculation table 5-2: theoretical step voltage (v s ) ( 1 ) note: when gain = 2 (v rl = v ref ), if v ref > v dd / 2, the v out voltage will be limited to v dd . so if v ref = v dd , then the v out voltage will not change for volatile dac register values mid-scale and greater, since the op amp is at full-scale output. where: # resistors in r-ladder = 4096 ( mcp47feb2x ) 1024 ( mcp47feb1x ) 256 ( mcp47feb0x ) v out v rl dac register value ? # resistor in resistor ladder --------------------------------------------------------------------- -gain ? = v ref 5.0 2.7 1.8 1.5 1.0 v s 1.22mv 659uv 439uv 366uv 244uv 12-bit 4.88mv 2.64mv 1.76mv 1.46mv 977uv 10-bit 19.5mv 10.5mv 7.03mv 5.86mv 3.91mv 8-bit note 1: when gain = 1x, v fs = v rl , and v zs = 0v. where: # resistors in r-ladder = 4096 ( 12-bit ) 1024 ( 10-bit ) 256 ( 8-bit ) v s v rl # resistor in resistor ladder --------------------------------------------------------------------- -gain ? = downloaded from: http:///
mcp47febxx ds20005375a-page 48 ? 2015 microchip technology inc. 5.3.4 output slew rate figure 5-6 shows an example of the slew rate of the v out pin. the slew rate can be affected by the charac- teristics of the circuit connected to the v out pin. figure 5-6: v out pin slew rate. 5.3.4.1 small capacitive load with a small capacitive load, the output buffers current is not affected by the capacitive load (c l ). but still, the v out pins voltage is not a step transition from one out- put value (dac register value) to the next output value. the change of the v out voltage is limited by the output buffers characteristics, so the v out pin voltage will have a slope from the old voltage to the new voltage. this slope is fixed for the output buffer, and is referred to as the buffer slew rate (sr buf ). 5.3.4.2 large capacitive load with a larger capacitive load, the slew rate is determined by two factors: the output buffers short-circuit current (i sc ) the v out pins external load i out cannot exceed the output buffers short-circuit cur- rent (i sc ), which fixes the output buffer slew rate (sr buf ). the voltage on the capacitive load (c l ), v cl , changes at a rate proportional to i out , which fixes a capacitive load slew rate (sr cl ). so the v cl voltage slew rate is limited to the slower of the output buffers internally set slew rate (srbuf) and the capacitive load slew rate (sr cl ). 5.3.5 driving resistive and capacitive loads the v out pin can drive up to 100 pf of capacitive load in parallel with a 5 k ? resistive load (to meet electrical specifications). a v out vs. resistive load characteri- zation graph can be seen in the char data for this device ( ds20005378 ). v out drops slowly as the load resistance decreases after about 3.5 k ? . it is recommended to use a load with r l greater than 5 k ? . driving large capacitive loads can cause stability problems for voltage feedback op amps. as the load capacitance increases, the feedback loops phase margin decreases and the closed-loop bandwidth is reduced. this produces gain peaking in the frequency response with overshoot and ringing in the step response. that is, since the v out pins voltage does not quickly follow the buffers input voltage (due to the large capacitive load), the output buffer will overshoot the desired target voltage. once the driver detects this overshoot, it compensates by forcing it to a voltage below the target. this causes voltage ringing on the v out pin. so, when driving large capacitive loads with the output buffer, a small series resistor (r iso ) at the output (see figure 5-7 ) improves the output buffers stability (feedback loops phase margin) by making the output load resistive at higher frequencies. the bandwidth will be generally lower than the bandwidth with no capacitive load. figure 5-7: circuit to stabilize output buffer for large capacitive loads (c l ). the r iso resistor value for your circuit needs to be selected. the resulting frequency response peaking and step response overshoot for this r iso resistor value should be verified on the bench. modify the r iso s resistance value until the output characteristics meet your requirements. a method to evaluate the systems performance is to inject a step voltage on the v ref pin and observe the v out pins characteristics. time dacx = a v out v out(a) v out(b) dacx= b slew rate v out b ?? v out a ?? C ? t -------------------------------------------------- = note: additional insight into circuit design for driving capacitive loads can be found in an884 C driving capacitive loads with op amps (ds00000884). v out op amp v w c l r iso r l v cl downloaded from: http:///
? 2015 microchip technology inc. ds20005375a-page 49 mcp47febxx table 5-3: dac input code vs. calculated analog output (v out ) (v dd = 5.0v) device volatile dac register value v rl ( 1 ) lsb gain selection ( 2 ) v out ( 3 ) equation v equation v mcp47feb2x (12-bit) 1111 1111 1111 5.0v 5.0v/4096 1,220.7 1x v rl ? (4095/4096) ? 1 4.998779 2.5v 2.5v/4096 610.4 1x v rl ? (4095/4096) ? 1 2.499390 2x ( 2 ) v rl ? (4095/4096) ? 2) 4.998779 0111 1111 1111 5.0v 5.0v/4096 1,220.7 1x v rl ? (2047/4096) ? 1) 2.498779 2.5v 2.5v/4096 610.4 1x v rl ? (2047/4096) ? 1) 1.249390 2x ( 2 ) v rl ? (2047/4096) ? 2) 2.498779 0011 1111 1111 5.0v 5.0v/4096 1,220.7 1x v rl ? (1023/4096) ? 1) 1.248779 2.5v 2.5v/4096 610.4 1x v rl ? (1023/4096) ? 1) 0.624390 2x ( 2 ) v rl ? (1023/4096) ? 2) 1.248779 0000 0000 0000 5.0v 5.0v/4096 1,220.7 1x v rl ? (0/4096) * 1) 0 2.5v 2.5v/4096 610.4 1x v rl ? (0/4096) * 1) 0 2x ( 2 ) v rl ? (0/4096) * 2) 0 mcp47feb1x (10-bit) 11 1111 1111 5.0v 5.0v/1024 4,882.8 1x v rl ? (1023/1024) ? 1 4.995117 2.5v 2.5v/1024 2,441.4 1x v rl ? (1023/1024) ? 1 2.497559 2x ( 2 ) v rl ? (1023/1024) ? 24 . 9 9 5 1 1 7 01 1111 1111 5.0v 5.0v/1024 4,882.8 1x v rl ? (511/1024) ? 1 2.495117 2.5v 2.5v/1024 2,441.4 1x v rl ? (511/1024) ? 1 1.247559 2x ( 2 ) v rl ? (511/1024) ? 22 . 4 9 5 1 1 7 00 1111 1111 5.0v 5.0v/1024 4,882.8 1x v rl ? (255/1024) ? 1 1.245117 2.5v 2.5v/1024 2,441.4 1x v rl ? (255/1024) ? 1 0.622559 2x ( 2 ) v rl ? (255/1024) ? 2 1.245117 00 0000 0000 5.0v 5.0v/1024 4,882.8 1x v rl ? (0/1024) ? 1 0 2.5v 2.5v/1024 2,441.4 1x v rl ? (0/1024) ? 1 0 2x ( 2 ) v rl ? (0/1024) ? 10 mcp47feb0x (8-bit) 1111 1111 5.0v 5.0v/256 19,531.3 1x v rl ? (255/256) ? 1 4.980469 2.5v 2.5v/256 9,765.6 1x v rl ? (255/256) ? 1 2.490234 2x ( 2 ) v rl ? (255/256) ? 2 4.980469 0111 1111 5.0v 5.0v/256 19,531.3 1x v rl ? (127/256) ? 1 2.480469 2.5v 2.5v/256 9,765.6 1x v rl ? (127/256) ? 1 1.240234 2x ( 2 ) v rl ? (127/256) ? 2 2.480469 0011 1111 5.0v 5.0v/256 19,531.3 1x v rl ? (63/256) ? 1 1.230469 2.5v 2.5v/256 9,765.6 1x v rl ? (63/256) ? 1 0.615234 2x ( 2 ) v rl ? (63/256) ? 2 1.230469 0000 0000 5.0v 5.0v/256 19,531.3 1x v rl ? (0/256) ? 1 0 2.5v 2.5v/256 9,765.6 1x v rl ? (0/256) ? 1 0 2x ( 2 ) v rl ? (0/256) ? 20 note 1: v rl is the resistor ladders reference voltage. it is independent of vref1:vref0 selection. 2: gain selection of 2x (gx = 1 ) requires voltage reference source to come from v ref pin (vref1:vref0 = 10 or 11 ) and requires v ref pin voltage (or v rl ) v dd /2 or from the internal band gap (vref1:vref0 = 01 ). 3: these theoretical calculations do not take into account the offset, gain and nonlinearity errors. downloaded from: http:///
mcp47febxx ds20005375a-page 50 ? 2015 microchip technology inc. 5.4 internal band gap the internal band gap is designed to drive the resistor ladder buffer. the resistance of a resistor ladder (r rl ) is targeted to be 140 k ? ( ? 40 k ? ), which means a minimum resis- tance of 100 k ? . the band gap selection can be used across the v dd voltages while maximizing the v out voltage ranges. for v dd voltages below the 2 ? gain ? v bg voltage, the output for the upper codes will be clipped to the v dd voltage. tab l e 5 - 4 shows the maximum dac register code given device vdd and gain bit setting. table 5-4: v out using band gap v dd dac gain max dac code ( 1 ) comment 12- bit 10-bit 8-bit 5.5 1 fffh 3ffh ffh v out(max) = 2.44v ( 3 ) 2 fffh 3ffh ffh v out(max) = 4.88v ( 3 ) 2.7 1 fffh 3ffh ffh v out(max) = 2.44v ( 3 ) 2 8dah 236h 8dh ~ 0 to 55% range 2.0 ( 4 ) 1 d1dh 347h d1h ~ 0 to 82% range 2 ( 2 ) 68eh 1a3h 68h ~ 0 to 41% range note 1: without the v out pin voltage being clipped. 2: recommended to use gain = 1 setting. 3: when v bg = 1.22v typical. 4: band gap performance achieves full performance starting from a v dd of 2.0v. downloaded from: http:///
? 2015 microchip technology inc. ds20005375a-page 51 mcp47febxx 5.5 latch pin (lat ) the latch pin controls when the volatile dac register value is transferred to the dac wiper. this is useful for applications that need to synchronize the wiper(s) updates to an external event, such as zero crossing or updates to the other wipers on the device. the lat pin is asynchronous to the serial interface operation. when the lat pin is high, transfers from the volatile dac register to the dac wiper are inhibited. the volatile dac register value(s) can be continued to be updated. when the lat pin is low, the volatile dac register value is transferred to the dac wiper. figure 5-8 shows the interaction of the lat pin and the loading of the dac wiper x (from the volatile dac reg- ister x). the transfers are level driven. if the lat pin is held low, the corresponding dac wiper is updated as soon as the volatile dac register value is updated. figure 5-8: lat and dac interaction. the lat pin allows the dac wiper to be updated to an external event as well as have multiple dac chan- nels/devices update at a common event. since the dac wiper x is updated from the volatile dac register x, all dacs that are associated with a given lat pin can be updated synchronously. if the application does not require synchronization, then this signal should be tied low. figure 5-9 shows two cases of using the lat pin to control when the wiper register is updated relative to the value of a sine wave signal. figure 5-9: example use of lat pin operation. note: this allows both the volatile dac0 and dac1 registers to be updated while the lat pin is high, and to have outputs syn- chronously updated as the lat pin is driven low. write command register address vol. dac register x dac wiper x 16 clocks lat sync transfer serial shift reg data (internal signal) lat sync transfer data comment 11 0 no transfer 10 0 no transfer 01 1 vol. dac register x ? dac wiper x 00 0 no transfer case 1: zero crossing of sine wave to update volatile dac0 register (using lat pin) case 2: fixed point crossing of sine wave to update volatile dac0 register (using lat pin) indicates where lat pin pulses active (volatile dac0 register updated) downloaded from: http:///
mcp47febxx ds20005375a-page 52 ? 2015 microchip technology inc. 5.6 power-down operation to allow the application to conserve power when the dac operation is not required, three power-down modes are available. the power-down configuration bits (pd1:pd0) control the power-down operation ( figure 5-10 and ta b l e 5 - 5 ). on devices with multiple dacs, each dacs power-down mode is individually controllable. all power-down modes do the following: turn off most the dac modules internal circuits (output op amp, resistor ladder,...) op amp output becomes high-impedance to the v out pin disconnects resistor ladder from reference voltage (v rl ) retains the value of the volatile dac register and configuration bits, and the nonvolatile (eeprom) dac register and configuration bits depending on the selected power-down mode, the following will occur: v out pin is switched to one of two resistive pull- downs (see tab le 5 -5 ) -100k ? (typical) -1k ? (typical) op amp is powered-down and the v out pin is high-impedance. there is a delay (t pde ) between the pd1:pd0 bits changing from 00 to either 01 , 10 or 11 and the op amp no longer driving the v out output and the pull- down resistors sinking current. in any of the power-down modes where the v out pin is not externally connected (sinking or sourcing current), the power-down current will typically be ~650 na for a single-dac device. as the number of dacs increases, the devices power-down current will also increase . the power-down bits are modified by using a write command to the volatile power-down register, or a por event which transfers the nonvolatile power-down reg- ister to the volatile power-down register. section 7.0 device commands describes the i 2 c commands for writing the power-down bits. the commands that can update the volatile pd1:pd0 bits are: write command (normal and high-voltage) read command (normal and high-voltage) enable configuration bit (high-voltage) disable configuration bit (high-voltage) general call reset general call wake-up figure 5-10: v out power-down block diagram. table 5-6 shows the current sources for the dac based on the selected source of the dacs reference voltage and if the device is in normal operating mode or one of the power-down modes. note: the i 2 c serial interface circuit is not affected by the power-down mode. this circuit remains active in order to receive any command that might come from the i 2 c master device. table 5-5: power-down bits and output resistive load pd1 pd0 function 00 normal operation 01 1k ? resistor to ground 10 100 k ? resistor to ground 11 open circuit table 5-6: dac current sources device v dd current source pd1:0 = 00 , vref1:0 = pd1:0 ? 00 , vref1:0 = 00 01 10 11 00 01 10 11 output op amp yy y ynn n n resistor ladder yyn ( 1 ) ynnn ( 1 ) n rl op amp n y n y n n n n band gap n y n n n y n n note 1: current is sourced from the v ref pin, not the device v dd . + - gain ( 1 ) v out 1 k 100 k pd1:pd0 v dd pd1:pd0 v w noe 1: gain options are 1 and 2. downloaded from: http:///
? 2015 microchip technology inc. ds20005375a-page 53 mcp47febxx 5.6.1 exiting power-down when the device exits the power-down mode the following occurs: disabled circuits (op amp, resistor ladder, ...) are turned on resistor ladder is connected to selected reference voltage (v rl ) selected pull-down resistor is disconnected the v out output will be driven to the voltage represented by the volatile dac registers value and configuration bits the v out output signal will require time as these circuits are powered-up and the output voltage is driven to the specified value as determined by the volatile dac register and configuration bits. the following events will change the pd1:pd0 bits to 00 and therefore exit the power-down mode. these are: any i 2 c write command where the pd1:pd0 bits are 00 . i 2 c general call wake-up command. i 2 c general call reset command. (if nonvolatile pd1:pd0 bits are 00 ). 5.6.2 reset commands when the mcp47febxx is in the valid operating volt- age, the i 2 c general call reset command will force a reset event. this is similar to the power-on reset, except that the reset delay timer is not started. if the i 2 c interface bus does not seem to be respon- sive, the technique shown in section 8.9 software i 2 c interface reset sequence can be used to force the i 2 c interface to be reset. 5.7 dac registers, configuration bits, and status bits the mcp47febxx devices have both volatile and nonvolatile (eeprom) memory. ta b l e 4 - 2 shows the volatile and nonvolatile memory and their interaction due to a por event. there are five configuration bits in both the volatile and nonvolatile memory, the dac registers in both the volatile and nonvolatile memory, and two volatile status bits. the dac registers (volatile and nonvolatile) will be either 12 bits (mcp47feb2x), 10 bits (mcp47feb1x), or 8 bits (mcp47feb0x) wide. when the device is first powered-up, it automatically uploads the eeprom memory values to the volatile memory. the volatile memory determines the analog output (v out ) pin voltage. after the device is powered- up, the user can update the device memory. the i 2 c interface is how this memory is read and written. refer to section 6.0 i 2 c serial interface module and section 7.0 device commands for more details on reading and writing the devices memory. when the nonvolatile memory is written, the device starts writing the eeprom cell at the acknowledge pulse of the write command. register 4-4 shows the operation of the device status bits, table 4-3 and tab l e 4 - 4 show the operation of the device configuration bits, and table 4-2 shows the fac- tory default value of a por/bor event for the device configuration bits. there are two status bits. these are only in volatile memory and give indication on the status of the device. the por bit indicates if the device v dd is above or below the por trip point. during normal operation, this bit should be 1 . the rdy/bsy bit indicates if an eeprom write cycle is in progress. while the rdy/bsy bit is low (during the eeprom writing), all commands are ignored, except for the read command. note: since the op amp and resistor ladder were powered-off (0v), the op amps input voltage (v w ) can be considered 0v. there is a delay (t pdd ) between the pd1:pd0 bits updating to 00 and the op amp driv- ing the v out output. the op amps settling time (from 0v) needs to be taken into account to ensure the v out voltage reflects the selected value. downloaded from: http:///
mcp47febxx ds20005375a-page 54 ? 2015 microchip technology inc. 6.0 i 2 c serial interface module the mcp47febxxs i 2 c serial interface module sup- ports the i 2 c serial protocol specification. this i 2 c interface is a two-wire interface (clock and data). figure 6-1 shows a typical i 2 c interface connection. the i 2 c specification only defines the field types, field lengths, timings, etc. of a frame. the frame content defines the behavior of the device. the frame content (commands) for the mcp47febxx is defined in section 7.0 device commands . an overview of the i 2 c protocol is available in section appendix b: i 2 c serial interface . figure 6-1: typical i 2 c interface. 6.1 overview this sections discusses some of the specific characteris- tics of the mcp47febxxs i 2 c serial interface module. this is to assist in the development of your application. the following sections discuss some of these device- specific characteristics. interface pins (scl and sda) communication data rates por/bor device memory address general call commands device i 2 c slave addressing entering high-speed (hs) mode 6.2 interface pins (scl and sda) the mcp47febxx i 2 cs module scl pin does not generate the serial clock since the device operates in slave mode. also, the mcp47febxx will not stretch the clock signal (scl) since memory read access occurs fast enough. the mcp47febxx i 2 cs module implements slope control on the sda pin output driver. 6.3 communication data rates the i 2 c interface specifies different communication bit rates. these are referred to as standard, fast or high- speed modes. the mcp47febxx supports these three modes. the clock rates (bit rate) of these modes are: standard mode: up to 100 khz (kbit/s) fast mode: up to 400 khz (kbit/s) high-speed mode (hs mode): up to 3.4 mhz (mbit/s) a description on how to enter high-speed mode is described in section 6.9 entering high-speed (hs) mode . 6.4 por/bor on a por/bor event, the i 2 c serial interface module state machine is reset, which includes that the devices memory address pointer is forced to 00h. 6.5 device memory address the memory address is the 5-bit value that specifies the location in the devices memory that the specified command will operate on. on a por/bor event, the devices memory address pointer is forced to 00h. the mcp47febxx retains the last device memory address that it has received. that is, the mcp47febxx does not corrupt the device memory address after repeated start or stop conditions. 6.6 general call commands the general call commands utilize the i 2 c specification reserved general call command address and command codes. the mcp47febxx also imple- ments a non-standard general call command. the general call commands are general call reset general call wake-up (mcp47febxx defined) the general call wake-up command will cause all the mcp47febxx devices to exit their power-down state. 6.7 multi-master systems the mcp47febxx is not a master device (generate the interface clock), but can be used in multi-master applications. scl scl mcp47febxx sda sda host controller typical i 2 c? interface connections other devices (master) (slave) downloaded from: http:///
? 2015 microchip technology inc. ds20005375a-page 55 mcp47febxx 6.8 device i 2 c slave addressing the mcp47febxx implements 7-bit slave addressing. the address byte is the first byte received following the start condition from the master device (see figure 6-2 ). the slave address is implemented in a nonvolatile reg- ister ( register 4-5 ) which is protected from accidental register writes via the slave address lock (salck) configuration bit. the salck configuration bit requires a high voltage (v ihh ) to be modified. the salck con- figuration bit must be disabled (see section 7.6 dis- able configuration bit (high-voltage) ) before a write to the nonvolatile slave addresses register can modify the value. figure 6-2: slave address bits in the i 2 c control byte. table 6-1 shows the four standard order-able i 2 c slave addresses and their respective device order code. 6.8.0.1 custom i 2 c slave address options custom i 2 c slave address options can be requested. customers can request the custom i 2 c slave address via the non-standard customer authorization request (nscar) process. note: after modifying the nonvolatile slave address value ( register 4-5 ), it is strongly recommended that the salck configuration bit is enabled (see section 7.5 enable configuration bit (high-voltage) ). note: the i 2 c 10-bit addressing mode is not supported. start bit read/write bit address byte r/w ack acknowledge bit slave address a6 a5 a4 a3 slave address (7-bits) a2 a1 a0 note 1: address bits (a6:a0) can be repro- grammed by the customer (nonvolatile device), but must unlock the slave address with a high-voltage command. 1100 000 a0 address ( 1 ) table 6-1: i 2 c address/order code 7-bit i 2 c? address device order code ( 1 ) comment 1100000 ( 2 ) mcp47febxxa0-e/st mcp47febxxa0t-e/st tape and reel 1100001 ( 2 ) mcp47febxxa1-e/st mcp47febxxa1t-e/st tape and reel 1100010 ( 2 ) mcp47febxxa2-e/st mcp47febxxa2t-e/st tape and reel 1100011 ( 2 ) mcp47febxxa3-e/st mcp47febxxa3t-e/st tape and reel note 1: xx in the order code indicates the resolu- tion and number of output channels for the device. 2: the devices i 2 c slave address can be reprogrammed by the end user. note 1: non-recurring engineering (nre) charges and minimum ordering requirements for custom orders. please contact microchip sales for additional information. 2: a custom device will be assigned custom device marking. downloaded from: http:///
mcp47febxx ds20005375a-page 56 ? 2015 microchip technology inc. 6.9 entering high-speed (hs) mode the i 2 c specification requires that a high-speed mode device must be activated to operate in high-speed (3.4 mbit/s) mode. this is done by the master sending a special address byte following the start bit. this byte is referred to as the high-speed master mode code (hsmmc). the device can now communicate at up to 3.4 mbit/s on sda and scl lines. the device will switch out of the hs mode on the next stop condition. the master code is sent as follows: 1. start condition (s) 2. high-speed master mode code ( 0000 1xxx ), the xxx bits are unique to the high-speed (hs) mode master. 3. no acknowledge (a ) after switching to the high-speed mode, the next transferred byte is the i 2 c control byte, which specifies the device to communicate with, and any number of data bytes plus acknowledgments. the master device can then either issue a repeated start bit to address a different device (at high-speed) or a stop bit to return to fast/standard bus speed. after the stop bit, any other master device (in a multi-master system) can arbitrate for the i 2 c bus. the mcp47febxx device does not acknowledge the hs select byte. however, upon receiving this com- mand, the device switches to hs mode. see figure 6-3 for illustration of hs mode command sequence. for more information on the hs mode, or other i 2 c modes, please refer to the nxp i 2 c specification. 6.9.1 slope control the slope control on the sda output is different between the fast/standard speed and the high-speed clock modes of the interface. 6.9.2 pulse gobbler the pulse gobbler on the scl pin is automatically adjusted to suppress spikes <10 ns during hs mode. figure 6-3: hs mode sequence. s a 0000 1xxxb sr a slave address a /a data p s = start bit sr = repeated start bit a = acknowledge bit a = not acknowledge bit r/w = read/write bit r/w p = stop bit (stop condition terminates hs mode) f/s-mode hs-mode hs-mode continues f/s-mode sr a slave address r/w hs select byte control byte command/data byte(s) control byte downloaded from: http:///
? 2015 microchip technology inc. ds20005375a-page 57 mcp47febxx 7.0 device commands this section documents the commands that the device supports. the commands can be grouped into the following categories: write command (normal and high-voltage) (c1:c0 = 00 ) read command (normal and high-voltage) (c1:c0 = 11 ) general call commands modify device configuration bit commands (hvc = v ihh ) - enable configuration bit (c1:c0 = 10 ) - disable configuration bit (c1:c0 = 01 ) the supported commands are shown in ta b l e 7 - 1 . these commands allow for both a single data or continuous data operation. continuous data operation means that the i 2 c master does not generate a stop bit but repeats the required data/clocks. this allows faster updates since the overhead of the i 2 c control byte is removed. table 7-1 also shows the required number of bit clocks for each commands different mode of operation. 7.0.1 aborting a transmission a restart or stop condition in an expected data bit position will abort the current command sequence and if the command was a write, that data word will not be written to the mcp47febxx. also the i 2 c state machine will be reset. if the condition was a restart (start), then the following byte will be expected to be the slave address byte. if the condition was a stop, the device will monitor for the start condition. table 7-1: device commands - number of clocks command # of bit clocks ( 1 ) data update rate (8-bit/10-bit/12-bit) (data words/second) comments operation code hv mode ( 6 ) c1 c0 100khz 400khz 3.4mhz ( 5 ) write command (normal and high- voltage) 00 ( 3 ) single 38 2,632 10,526 89,474 00 ( 3 ) continuous 27n + 11 3,559 14,235 120,996 for 10 data words read command (nor- mal and high-voltage) ( 2 ) 11 ( 3 ) random 48 2,083 8,333 70,833 11 ( 3 ) continuous 18n + 11 4,762 19,048 161,905 for 10 data words 11 ( 3 ) last address 29 3,448 13,793 117,241 general call reset command ( 3 ) single 20 5,000 20,000 170,000 note 4 general call wake-up command ( 3 ) single 20 5,000 20,000 170,000 note 4 enable configuration bit (high-voltage) command 10 yes single 20 5,000 20,000 170,000 10 yes continuous 9n + 11 9,901 39,604 336,634 for 10 data words disable configuration bit (high-voltage) command 01 yes single 20 5,000 20,000 170,000 01 yes continuous 9n + 11 9,901 39,604 336,634 for 10 data words note 1: n indicates the number of times the command operation is to be repea ted. 2: this command is useful to determine when an eeprom programming cycle has completed. 3: this command can be either normal voltage or high voltage. 4: determined by general call command byte after the i 2 c general call address. 5: there is a minimal overhead to enter into 3.4 mhz mode. 6: nonvolatile registers can only use the single mode. downloaded from: http:///
mcp47febxx ds20005375a-page 58 ? 2015 microchip technology inc. 7.1 write command (normal and high-voltage) write commands are used to transfer data to the desired memory location (from the host controller). the write command can be issued to both the volatile and nonvolatile memory locations. write commands can be structured as either single or continuous. the continuous format allows the fastest data update rate for the devices memory locations, but is not supported for nonvolatile memory locations. the format of the command is shown in figure 7-1 (single) and figure 7-3 (continuous). for example ack/nack behavior see figure 7-2 . a write command to a volatile memory location changes that location after a properly formatted write command and the a/a clock has been received. a write command to a nonvolatile memory location will start an eeprom write cycle only after a properly formatted write command has been received and the stop condition has occurred. 7.1.1 single write to volatile memory for volatile memory locations, data is written to the mcp47febxx after every data word transfer (during the acknowledge). if a stop or restart condition is generated during a data transfer (before the a), the data will not be written to the mcp47febxx. after the a bit, the master can initiate the next sequence with a stop or restart condition. refer to figure 7-1 for the byte write sequence. 7.1.2 single write to nonvolatile memory the sequence to write to a single nonvolatile memory location is the same as a single write to volatile memory with the exception that the eeprom write cycle (t wc ) is started after a properly formatted command, includ- ing the stop bit, is received. after the stop condition occurs, the serial interface may immediately be re-enabled by initiating a start condition. during an eeprom write cycle, access to the volatile memory is allowed when using the appropriate com- mand sequence. commands that address nonvolatile memory are ignored until the eeprom write cycle (t wc ) completes. this allows the host controller to operate on the volatile dac registers. figure 7-1 shows the waveform for a single write. figure 7-1: write random address command (volatile and nonvolatile memory). note 1: writes to certain memory locations will be dependent on the state of the wiperlock technology status bits. 2: during device communication, if the device address/command combination is invalid or an unimplemented device address is specified, then the mcp47febxx will nack that byte. to reset the i 2 c state machine, the i 2 c communication must detect a start bit. note: the eewa status bit indicates if an eeprom write cycle is active (see register 4-4 ). control byte write command sa s0 ad ad ad ad ad a0 0 x a 1 2 3 4 i 2 c? slave address memory address command write bit reserved 0 write data a d dddd ddd ap write data bits 00 01 02 03 04 05 06 07 d dddd ddd 08 09 10 11 12 13 14 15 6 sa 5 sa 4 sa 3 sa 2 sa 1 sa 0 start bit ack bit ( 1 ) ack bit ( 1 , 2 ) ack bit (1) ack bit ( 1 , 2 ) stop bit ( 2 ) note 1: the acknowledge bit is generated by the mcp47febxx. 2: at the falling edge of the scl pin for the write command ack bit, the mcp47febxx device updates the value of the specified device register. 3: this command sequence does not need to terminate (using the stop bit), and the write command can be repeated (see continuous write format, section 7.1.3 continuous writes to volatile memory ). downloaded from: http:///
? 2015 microchip technology inc. ds20005375a-page 59 mcp47febxx 7.1.3 continuous writes to volatile memory a continuous write mode of operation is possible when writing to the devices volatile memory registers (see table 7-1 ). this continuous write mode allows writes without a stop or restart condition or repeated trans- missions of the i 2 c control byte. figure 7-3 shows the sequence for three continuous writes. the writes do not need to be to the same volatile memory address. the sequence ends with the master sending a stop or restart condition. 7.1.4 continuous writes to nonvolatile memory if a continuous write is attempted on nonvolatile memory, the missing stop condition will cause the command to be an error condition (a ). a start bit is required to reset the command state machine. 7.1.5 the high voltage command (hvc) signal the high voltage command (hvc) signal is used to indicate that the command, or sequence of com- mands, are in the high voltage operational state. high voltage commands allow the devices wiperlock technology and write protect features to be enabled and disabled. figure 7-2: i 2 c ack / nack behavior (write command example). table 7-1: volatile memory addresses address single-channel dual-channel 00h yes yes 01h no yes 08h yes yes 09h yes yes 0ah yes yes note: writes to a volatile dac register will not transfer to the output register until the lat (hvc) pin is transitioned from the v ihhen voltage to a v il voltage. write 1 byte command sslave address r/w ack command ack data byte ack data byte ack p master s s a6 sa 5 sa 4 sa 3 sa 2 sa 1 sa 0 01a d4 ad 3 ad 2 ad 1 ad 0 c1 c0 xa ck d1 5 d1 4 d1 3 d1 2 d1 1 d1 0 d0 9 d0 8 1d 07 d0 6 d0 5 d0 4 d0 3 d0 2 d0 1 d0 0 1p example 1 (no command error) master s1100000010000100x1dddddddd1dddddddd1p mcp47febxxa0 0 0 0 0 i 2 c? buss1100000000000100x0dddddddd0dddddddd0p example 2 (command error) master s1100000010111100x1dddddddd1dddddddd1p mcp47febxxa0 0 1 1 1 i 2 c bus s1100000000111100x0dddddddd1dddddddd1p note: once a command error has occurred (example 2), the mcp47febxx will nack until a start condition occurs. downloaded from: http:///
mcp47febxx ds20005375a-page 60 ? 2015 microchip technology inc. figure 7-3: continuous write commands (volatile memory only). control byte write command s0 ad ad ad ad ad a0 0 x a 1 2 3 4 i 2 c? slave address memory address command reserved 0 write data a d dddd ddd a write data bits 00 01 02 03 04 05 06 07 d dddd ddd 08 09 10 11 12 13 14 15 write data a d dddd ddd a write data bits 00 01 02 03 04 05 06 07 d dddd ddd 08 09 10 11 12 13 14 15 write command ad ad ad ad ad 00 x a 1 2 3 4 device memory address command reserved 0 write data a d dddd ddd ap write data bits 00 01 02 03 04 05 06 07 d dddd ddd 08 09 10 11 12 13 14 15 write command ad ad ad ad ad 00 x a 1 2 3 4 device memory address command reserved 0 sa 6 sa 5 sa 4 sa 3 sa 2 sa 1 sa 0 write bit start bit ack bit ( 1 ) ack bit ( 1 , 2 ) ack bit ( 1 ) ack bit ( 1 , 2 ) ack bit ( 1 , 2 ) stop bit ( 3 ) ack bit ( 1 ) ack bit ( 1 , 2 ) ack bit ( 1 ) ack bit ( 1 ) ack bit ( 1 ) note 1: the acknowledge bit is generated by the mcp47febxx. 2: at the falling edge of the scl pin for the write command ack bit, the mcp47febxx device updates the value of the specified device register. 3: this command sequence does not need to terminate (using the stop bit), and the write command can be repeated (see continuous write format, section 7.1.3 continuous writes to volatile memory ). 4: only functions when writing to volatile registers (ad4:ad0 = 00h through 0ah). downloaded from: http:///
? 2015 microchip technology inc. ds20005375a-page 61 mcp47febxx 7.2 read command (normal and high-voltage) read commands are used to transfer data from the specified memory location (to the host controller). the read command can be issued to both the volatile and nonvolatile memory locations. during an eeprom write cycle (write to nonvolatile memory location or enable/disable configura- tion bit command) the read command can only read the volatile memory locations. by reading the sta- tus register (0ah), the host controller can determine when the write cycle has completed (via the state of the eewa bit). the read command formats include: single read - single memory address - last memory address accessed continuous reads the mcp47febxx retains the last device memory address that it has received. that is the mcp47febxx does not corrupt the device memory address after repeated start or stop conditions. if the address pointer is for a nonvolatile memory loca- tion and it is during a nonvolatile write cycle (t wc ) the mcp47febxx will respond with an a bit. 7.2.1 single read the read command format writes two bytes, the con- trol byte and the read command byte (desired memory address and the read command), and then has a restart condition. then a 2 nd control byte is transmit- ted, but this control byte indicates a i 2 c read operation (r/w bit = 1 ). 7.2.1.1 single memory address figure 7-4 shows the sequence for reading a specified memory address. 7.2.1.2 last memory address accessed figure 7-5 shows the waveforms for a single read of the last memory location accessed. this command allows faster communication when checking the status of the eeprom write active (eewa) bit (see register 4-4 ), as long as the register address of this devices last command was 0ah. 7.2.2 continuous reads continuous reads allows the devices memory to be read quickly. continuous reads are possible to all memory locations. if a nonvolatile memory write cycle is occurring, then read commands may only access the volatile memory locations. figure 7-7 shows the sequence for three continuous reads. for continuous reads, instead of transmitting a stop or restart condition after the data transfer, the master continually reads the data byte. the sequence ends with the master not acknowledging and then sending a stop or restart. this is useful in reading the system status register (0ah) to determine if an eeprom write cycle has completed (eewa bit). 7.2.3 ignoring an i 2 c transmission and falling off the bus the mcp47febxx expects to receive complete, valid i 2 c commands and will assume any command not defined as a valid command is due to a bus corruption, thus entering a passive high condition on the sda sig- nal. all signals will be ignored until the next valid start condition and control byte are received. note 1: during device communication, if the device address/command combination is invalid or an unimplemented address is specified, then the mcp47febxx will nack that byte. to reset the i 2 c state machine, the i 2 c communication must detect a start bit. 2: if the lat pin is high (v ih ), reads of the volatile dac register read the output value, not the internal register. 3: the read commands operate the same regardless of the state of the high- voltage command (hvc) signal. downloaded from: http:///
mcp47febxx ds20005375a-page 62 ? 2015 microchip technology inc. figure 7-4: read command - single memory address. figure 7-5: read command - last memory address accessed. control byte read command s0 ad ad ad ad ad a1 1 x a s r 1 2 3 4 i 2 c? slave address memory address command control byte read bits d ddd d d dd a write bit d dddd ddd a 1a read bit repeated start bit read data bits 00 01 02 03 04 05 06 07 08 09 10 11 12 13 14 15 0 p sa 6 sa 5 sa 4 sa 3 sa 2 sa 1 sa 0 sa 6 sa 5 sa 4 sa 3 sa 2 sa 1 sa 0 i 2 c slave address start bit ack bit ( 1 ) ack bit ( 1 ) ack bit ( 4 ) ack bit ( 5 ) stop bit ( 2, 3 ) ack bit ( 1 ) note 1: the acknowledge bit is generated by the mcp47febxx. 2: at the falling edge of the scl pin for the read command ack bit, the mcp47febxx device updates the value of the specified device register. 3: this command sequence does not need to terminate (using the stop bit), and the read command can be repeated (see continuous read format, section 7.2.2 continuous reads ). 4: master device is responsible for a/a signal. if an a signal occurs, the mcp47febxx will abort this transfer and release the bus. 5: the master device will not acknowledge, and the mcp47febxx will release the bus so the master device can generate a stop or repeated start condition. control byte s1 a i 2 c? slave address read bits p d ddd d d dd a d dddd ddd a read data bits 00 01 02 03 04 05 06 07 08 09 10 11 12 13 14 15 sa 6 sa 5 sa 4 sa 3 sa 2 sa 1 sa 0 start bit ack bit ( 1 ) ack bit ( 2 ) read bit stop bit ( 5 ) ack bit ( 3 , 4 ) note 1: the acknowledge bit is generated by the mcp47febxx. 2: master device is responsible for a/a signal. if a a signal occurs, the mcp47febxx will abort this trans- fer and release the bus. 3: the master device will not acknowledge, and the mcp47febxx will release the bus so the master device can generate a stop or repeated start condition. 4: at the falling edge of the scl pin for the read command ack bit, the mcp47febxx device updates the value of the specified device register. 5: this command sequence does not need to terminate (using the stop bit), and the read command can be repeated (see continuous read format, section 7.2.2 continuous reads ). downloaded from: http:///
? 2015 microchip technology inc. ds20005375a-page 63 mcp47febxx figure 7-6: i 2 c ack/nack behavior (read command example). write 1 byte command sslave address r/ w ac k command ac k master s s a6 sa 5 sa 4 sa 3 sa 2 sa 1 sa 0 01a d4 ad 3 ad 2 ad 1 ad 0 c1 c0 x1 s r slave address r/ w ac kdata byte ac k data byte ac kp master (continued) s r sa 6 sa 5 sa 4 sa 3 sa 2 sa 1 sa 0 11d 15 d1 4 d1 3 d1 2 d1 1 d1 0 d0 9 d0 8 1d 07 d0 6 d0 5 d0 4 d0 3 d0 2 d0 1 d0 0 1p ex.1 (no command error) master s1100000010000111x1 mcp47febxxa0 0 0 i 2 c? buss1100000000000011x0 master (continued) s000010011 1 1p mcp47febxxa0 (continued) 0 d d d d d d d d 0 d d d d d d d d 0 i 2 c bus (continued) s000000010dddddddd0dddddddd0p ex.2 (with command error) master s1100000010111100x1 mcp47febxxa0 0 1 i 2 c bus s1100000000111100x1 master (continued) s110000011 1 1p mcp47febxxa0 (continued) 0 ? ? ? ? ? ? ? ? 0 ? ? ? ? ? ? ? ? 1 i 2 c bus (continued) s110000010????????0????????1p note 1: once a command error has occurred (example 2), the mcp47febxx will nack until a start condition occurs. 2: for command error case (example 2), the data read is from the register of the last valid address loaded into the device. downloaded from: http:///
mcp47febxx ds20005375a-page 64 ? 2015 microchip technology inc. figure 7-7: continuous read command of specified address. control byte read command s0 ad ad ad ad ad a1 1 x a s r 1 2 3 4 i 2 c? slave address memory address command control byte read bits d ddd d d dd a d dddd ddd a 1a read data bits 00 01 02 03 04 05 06 07 08 09 10 11 12 13 14 15 0 sa 6 sa 5 sa 4 sa 3 sa 2 sa 1 sa 0 sa 6 sa 5 sa 4 sa 3 sa 2 sa 1 sa 0 i 2 c slave address read bits d ddd d d dd a d dddd ddd a read data bits 00 01 02 03 04 05 06 07 08 09 10 11 12 13 14 15 read bits d ddd d d dd a d dddd ddd a read data bits 00 01 02 03 04 05 06 07 08 09 10 11 12 13 14 15 p write bit repeated start bit start bit ack bit ( 1 ) ack bit ( 1 ) read bit ack bit ( 4 ) ack bit ( 5 ) stop bit ( 2, 3 ) ack bit ( 1 ) ack bit ( 5 ) ack bit ( 4 ) ack bit ( 4 ) ack bit ( 5 ) note 1: the acknowledge bit is generated by the mcp47febxx. 2: at the falling edge of the scl pin for the read command ack bit, the mcp47febxx device updates the value of the specified device register. 3: this command sequence does not need to terminate (using the stop bit), and the read command can be repeated (see continuous read format, section 7.2.2 continuous reads ). 4: master device is responsible for a / a signal. if a a signal occurs, the mcp47febxx will abort this transfer and release the bus. 5: the master device will not acknowledge, and the mcp47febxx will release the bus so the master device can generate a stop or repeated start condition. downloaded from: http:///
? 2015 microchip technology inc. ds20005375a-page 65 mcp47febxx 7.3 general call commands the mcp47febxx acknowledges the general call address command (00h in the first byte). general call commands can be used to communicate to all devices on the i 2 c bus (at the same time) that understand the general call command. the meaning of the general call address is always specified in the second byte (see figure 7-8 ). if the second byte has a 1 in the lsb, the specification intends this to indicate a hardware general call. the mcp47febxx will ignore this byte and all following bytes (and a ), until a stop bit (p) is encountered. the mcp47febxx devices support the following i 2 c general call commands: general call reset (06h) general call wake-up (0ah) the general call reset command format is specified by the i 2 c specification. the general call wake-up command is a microchip-defined format. the general call wake-up command will have all devices wake-up (that is, exit the power-down mode). the other two i 2 c specification command codes (04h and 00h) are not supported, and therefore those commands are not acknowledged. if these 7-bit commands conflict with other i 2 c devices on the bus, then the customer will need two i 2 c buses and ensure that the devices are on the correct bus for their desired application functionality. figure 7-8: general call formats. note: refer to the nxp specification #um10204, rev. 03 19 june 2007 document for more details on the general call specifications. the i 2 c specification does not allow 00000000 (00h) in the second byte. 0 000 s 0000 x xxxx a xx0ap general call address second byte 7-bit command reserved 7-bit commands (by i 2 c? specification - nxp specification # um10204, rev. 03 19 june 2007) 0000 011 b - reset and write programmable part of slave address by hardware. 0000 010 b - write programmable part of slave address by hardware (not implemented). 0000 000 b - not allowed mcp47febxx 7-bit commands 0000 011 b - device reset (subset of i 2 c reserved command). 0000 101 b - dac output exit power-down state (pd1:pd0 = 00 ). the following is a hardware general call format 0 000 s0 0 0 0 x xxxx a xx1a general call address second byte 7-bit command x xxxx xxxap n occurrences of (data + a) this indicates a hardware general call mcp47febxx will ignore this byte and all following bytes (and a ), until a stop bit (p) is encountered. downloaded from: http:///
mcp47febxx ds20005375a-page 66 ? 2015 microchip technology inc. 7.3.1 general call reset the i 2 c general call reset command forces a reset event. this is similar to the power-on reset, except that the reset delay timer is not started. this command allows multiple mcp47febxx devices to be reset synchronously. the device performs general call reset if the second byte is 00000110 (06h). at the acknowledgment of this byte, the device will abort the current conversion and perform the following tasks: internal reset similar to a power-on reset (por). the contents of the eeprom are loaded into the dac registers and analog output is available immediately (following the acknowledgment pulse). the v out will be available immediately, but after a short time delay following the acknowledgment pulse. the v out value is determined by the eeprom contents. 7.3.2 general call wake-up the i 2 c general call wake-up command forces the device to exit from its power-down state (forces the pdxb:pdxa bits to 00 ). this command allows multiple mcp47febxx devices to wake-up synchronously. the device performs general call wake-up if the second byte (after the general call address) is 00001010 (0ah). at the acknowledgment of this byte, the device will perform the following task: the devices volatile power-down bits (pdxb:pdxa) are forced to 00 . the nonvolatile (eeprom) power-down bit values are not affected by this command. figure 7-9: general call reset command. figure 7-10: general call wake-up command. control byte general call reset command s0 a 1 1 0 a p general call address write bit note 1: the acknowledge bit is generated by the mcp47febxx. 2: at the falling edge of the scl pin for the general call wake-up command ack bit, the mcp47febxx device is reset. 3: this command sequence does not need to terminate (using the stop bit), and the general call wake-up command can be repeated, or the general call reset command can be sent. 0 0 0 0 0 0 00 0 0 0 0 start bit ack bit ( 1 ) ack bit ( 1 , 2 ) stop bit ( 3 ) control byte general call wake-up command s 0 a 0 1 0 a p general call address write bit note 1: the acknowledge bit is generated by the mcp47febxx. 2: at the falling edge of the scl pin for the general call wake-up command ack bit, the volatile power-down bits (pdxb:pdxa) are forced to 00 . 3: this command sequence does not need to terminate (using the stop bit), and the general call wake-up command can be repeated, or the general call reset command can be sent. 0 0 0 0 0 0 01 0 0 0 0 start bit ack bit ( 1 , 2 ) stop bit ( 3 ) ack bit ( 1 ) downloaded from: http:///
? 2015 microchip technology inc. ds20005375a-page 67 mcp47febxx 7.4 modify device configuration bit commands these commands are used to program the device configuration bits. these commands require a high voltage (v ihh ) on the hvc pin. the mcp47febxx devices support the modify device configuration bit commands: enable configuration bit (high-voltage) disable configuration bit (high-voltage) these configuration bits are used to inhibit the dac values from inadvertent modification. high voltage is required to change the state of these bits if/when the dac values need to be modified. 7.5 enable configuration bit (high-voltage) figure 7-11 (enable) shows the formats for a single modify write protect or wiper-lock tech- nology command. a modify write protect or wiper-lock tech- nology command will only start an eeprom write cycle (t wc ) after a properly formatted command has been received and the stop condition occurs. during an eeprom write cycle, only serial commands to volatile memory are accepted. all other serial com- mands are ignored until the eeprom write cycle (t wc ) completes. this allows the host controller to operate on the volatile dac, the volatile v ref , power-down, gain and status, and wiperlock technology status registers. the eewa bit in the status register indicates the status of an eeprom write cycle. 7.5.1 the high-voltage command (hvc) signal the high-voltage command (hvc) signal is used to indicate that the command, or sequence of commands, are in the high-voltage mode. signals >v ihh (~9.0v) on the hvc pin puts the device into high-voltage mode. high voltage commands allow the devices wiperlock technology and write-protect features to be enabled and disabled. figure 7-11: i 2 c enable command sequence. note 1: there is a required delay after the hvc pin is driven to the v ihh level to the 1 st edge of the scl pin. 2: the command sequence can go from an increment to any other valid command for the specified address. issuing an increment or decrement to a nonvolatile location will cause an error condition (a will be generated). control byte enable command enable command ( 3 ) s0 ad ad ad ad a1 0 x a ad ad ad ad 10 xap 1 2 3 4 4321 i 2 c? slave address ( 1 ) memory address command note 1: the slave address is determined by the nv gain and i 2 c 7-bit slave address register. the default factory address is 110 0000b (c0h for control byte with write, c1h for control byte with read). 2: this command sequence does not need to terminate (using the stop bit) and can change to any other desired command sequence ( disable , read or write ). 3: this command byte is not required and the stop bit may occur immediately after the 2 nd ack bit in this sequence. ad 0 ad 0 memory address command sa sa sa sa 1 2 3 4 sa 0 sa sa 5 6 write bit start bit ack bit ( 1 ) ack bit ( 1 , 2 ) ack bit ( 1 , 2 ) stop bit ( 2 ) downloaded from: http:///
mcp47febxx ds20005375a-page 68 ? 2015 microchip technology inc. 7.6 disable configuration bit (high-voltage) figure 7-12 (disable) shows the formats for a single modify write protect or wiper-lock technology command. a modify write protect or wiper-lock tech- nology command will only start an eeprom write cycle (t wc ) after a properly formatted command has been received and the stop condition occurs. during an eeprom write cycle, only serial commands to volatile memory are accepted. all other serial com- mands are ignored until the eeprom write cycle (t wc ) completes. this allows the host controller to operate on the volatile dac, the volatile v ref , power-down, gain and status, and wiperlock technology status registers. the eewa bit in the status register indicates the status of an eeprom write cycle. 7.6.1 the high-voltage command (hvc) signal the high voltage command (hvc) signal is used to indicate that the command, or sequence of commands, are in the high-voltage mode. signals >v ihh (~9.0v) on the hvc pin puts mcp47febxx devices into high- voltage mode. high voltage commands allow the devices wiperlock technology and write protect features to be enabled and disabled. figure 7-12: i 2 c disable command sequence. note 1: there is a required delay after the hvc pin is driven to the v ihh level to the 1 st edge of the scl pin. 2: the command sequence can go from an increment to any other valid command for the specified address. issuing an increment or decrement to a nonvolatile location will cause an error condition (a will be generated). control byte disable command disable command ( 3 ) s0 ad ad ad ad a0 1 x a ad ad ad ad 01 xap 1 2 3 4 4321 i 2 c? slave address (1) address command note 1: the slave address is determined by the nv gain and i 2 c 7-bits slave address register. the default factory address is 110 0000b (c0h for control byte with write, c1h for control byte with read). 2: this command sequence does not need to terminate (using the stop bit) and can change to any other desired command sequence ( enable , read or write ). 3: this command byte is not required and the stop bit may occur immediately after the 2 nd ack bit in this sequence. ad 0 ad 0 address command sa sa sa sa 1 2 3 4 sa 0 sa sa 5 6 write bit start bit ack bit ( 1 ) ack bit ( 1 , 2 ) ack bit ( 1 , 2 ) stop bit ( 2 ) downloaded from: http:///
? 2015 microchip technology inc. ds20005375a-page 69 mcp47febxx figure 7-13: configuring all user configuration bits command sequence (mcp47febx1). figure 7-14: configuring all user configuration bits command sequence (mcp47febx2). control byte s0 a 1 0 x a 1 0 x a i 2 c? slave address ( 1 ) address enable command write bit address enable command 0 0 0 0 0 1 10 0 0 0 00 0 0 0 1 10 xa 10 xap address enable command address enable command 0 1 0 1 11 1 0 1 1 dac 0 salck (cl:dl) note 1: the two command bits may either specify the enable command or the disable command. control byte s0 a 1 0 x a 1 0 x a i 2 c? slave address ( 1 ) address enable command write bit address enable command 0 0 0 0 0 1 10 0 0 0 00 0 0 0 1 10 xa 10 xap address enable command address enable command 0 1 0 1 11 1 0 1 1 10 x a 10 xa address enable command address enable command 1 0 0 0 01 0 0 0 1 dac 0 salck dac 1 (cl:dl) (cl:dl) note 1: the two command bits may either specify the enable command or the disable command. downloaded from: http:///
mcp47febxx ds20005375a-page 70 ? 2015 microchip technology inc. notes: downloaded from: http:///
? 2015 microchip technology inc. ds20005375a-page 71 mcp47febxx 8.0 typical applications the mcp47febxx family of devices are general pur- pose, single/dual-channel voltage output dacs for vari- ous applications where a precision operation with low-power and nonvolatile eeprom memory is needed. since the devices include a nonvolatile eeprom memory, the user can utilize these devices for applications that require the output to return to the previous set-up value on subsequent power-ups. applications generally suited for the devices are: set point or offset trimming sensor calibration portable instrumentation (battery-powered) motor control 8.1 connecting to i 2 c bus using pull-up resistors the scl and sda pins of the mcp47febxx devices are open-drain configurations. these pins require a pull-up resistor, as shown in figure 8-2 . the pull-up resistor values (r 1 and r 2 ) for scl and sda pins depend on the operating speed (standard, fast and high-speed) and loading capacitance of the i 2 c bus line. a higher value of the pull-up resistor consumes less power, but increases the signal transition time (higher rc time constant) on the bus line. therefore, it can limit the bus operating speed. the lower resistor value, on the other hand, consumes higher power, but allows higher operating speed. if the bus line has higher capacitance due to long metal traces or multiple device connections to the bus line, a smaller pull-up resistor is needed to compensate the long rc time constant. the pull-up resistor is typically chosen between 1 k ?? and 10 k ?? ranges for standard and fast modes, and less than 1 k ?? for high-speed mode. 8.1.1 device connection test the user can test the presence of the device on the i 2 c bus line using a simple i 2 c command. this test can be achieved by checking an acknowledge response from the device after sending a read or write command. figure 8-1 shows an example with a read command. the steps are: 1. set the r/w bit high in the devices address byte. 2. check the ack bit of the address byte. if the device acknowledges (ack = 0 ) the command, then the device is connected. otherwise, it is not connected. 3. send stop bit. figure 8-1: i 2 c bus connection test. 123456789 scl sda a2 a1 a0 1 start bit address byte address bits r/w stop bit device ack response a3 a4 a5 a6 downloaded from: http:///
mcp47febxx ds20005375a-page 72 ? 2015 microchip technology inc. 8.2 power supply considerations the power source should be as clean as possible. the power supply to the device is also used for the dac voltage reference internally if the internal v dd is selected as the resistor ladders reference voltage (vrxb:vrxa = 00 ). any noise induced on the v dd line can affect the dac performance. typical applications will require a bypass capacitor in order to filter out high-frequency noise on the v dd line. the noise can be induced onto the power supplys traces or as a result of changes on the dac out- put. the bypass capacitor helps to minimize the effect of these noise sources on signal integrity. figure 8-2 shows an example of using two bypass capacitors (a 10 f tantalum capacitor and a 0.1 f ceramic capaci- tor) in parallel on the v dd line. these capacitors should be placed as close to the v dd pin as possible (within 4 mm). if the application circuit has separate digital and analog power supplies, the v dd and v ss pins of the device should reside on the analog plane. figure 8-2: example circuit. analog v dd 12 3 86 v dd sda scl v ss v out0 7 r 1 r 2 to m c u r 1 and r 2 are i 2 c? pull-up resistors: r 1 and r 2 : 5k ? - 10 k ? for f scl = 100 khz to 400 khz ~700 ? for f scl = 3.4 mhz c 1 : 0.1 f capacitor ceramic c 2 : 10 f capacitor tantalum c 3 : ~ 0.1 f optional to reduce noise in v out pin. c 4 : 0.1 f capacitor ceramic c 5 : 10 f capacitor tantalum c 6 : 0.1 f capacitor ceramic c 2 c 1 mcp47febx2 optional (a) circuit when v dd is selected as reference ( note: v dd is connected to the reference circuit internally.) (b) circuit when external reference is used. output v ref 4 5 lat/hvc v out1 c 4 c 3 analog v dd 12 3 86 v dd sda scl v ss v out0 7 to m c u c 2 c 1 mcp47febx2 optional output v ref 4 5 lat/hvc v out1 c 5 optional v ref c 6 r 1 r 2 c 4 c 3 downloaded from: http:///
? 2015 microchip technology inc. ds20005375a-page 73 mcp47febxx 8.3 application examples the mcp47febxx devices are rail-to-rail output dacs designed to operate with a v dd range of 2.7v to 5.5v. the internal output op amplifier is robust enough to drive common, small-signal loads directly, thus eliminating the cost and size of external buffers for most applications. the user can use gain of 1 or 2 of the output op amplifier by setting the configuration register bits. also, the user can use internal v dd as the reference or use external reference. various user options and easy-to-use features make the devices suitable for various modern dac applications. application examples include: decreasing output step size building a window dac bipolar operation selectable gain and offset bipolar voltage output designing a double-precision dac building programmable current source serial interface communication times software i 2 c interface reset sequence power supply considerations layout considerations 8.3.1 dc set point or calibration a common application for the devices is a digitally-controlled set point and/or calibration of variable parameters, such as sensor offset or slope. for example, the mcp47feb2x provides 4096 output steps. if voltage reference is 4.096v (where gx = 0 ), the lsb size is 1 mv. if a smaller output step size is desired, a lower external voltage reference is needed. 8.3.1.1 decreasing output step size if the application is calibrating the bias voltage of a diode or transistor, a bias voltage range of 0.8v may be desired with about 200 v resolution per step. two common methods to achieve small step size are using lower v ref pin voltage or using a voltage divider on the dacs output. using an external voltage reference (v ref ) is an option if the external reference is available with the desired output voltage range. however, occasionally, when using a low-voltage reference voltage, the noise floor causes a snr error that is intolerable. using a voltage divider method is another option, and provides some advantages when external voltage reference needs to be very low, or when the desired output voltage is not available. in this case, a larger value reference voltage is used, while two resistors scale the output range down to the precise desired level. figure 8-3 illustrates this concept. a bypass capacitor on the output of the voltage divider plays a critical function in attenuating the output noise of the dac and the induced noise from the environment. figure 8-3: example circuit of set point or threshold calibration. equation 8-1: v out and v trip calculations r 1 v cc + v cc C v out i 2 c? 2-wire v ref optional mcp47febxx v dd v o r 2 c 1 r sense comp. v dd v trip v trip v out r 2 r 1 r 2 + -------------------- ?? ?? ?? = v out = v ref g dac register value 2 n downloaded from: http:///
mcp47febxx ds20005375a-page 74 ? 2015 microchip technology inc. 8.3.1.2 building a window dac when calibrating a set point or threshold of a sensor, typically only a small portion of the dac output range is utilized. if the lsb size is adequate enough to meet the applications accuracy needs, the unused range is sacrificed without consequences. if greater accuracy is needed, then the output range will need to be reduced to increase the resolution around the desired threshold. if the threshold is not near v ref , 2 v ref , or v ss , then creating a window around the threshold has several advantages. one simple method to create this window is to use a voltage divider network with a pull-up and pull-down resistor. figure 8-4 and figure 8-6 illustrate this concept. figure 8-4: single-supply window dac. equation 8-2: v out and v trip calculations 8.4 bipolar operation bipolar operation is achievable by utilizing an external operational amplifier. this configuration is desirable due to the wide variety and availability of op amps. this allows a general purpose dac, with its cost and availability advantages, to meet almost any desired output voltage range, power and noise performance. figure 8-5 illustrates a simple bipolar voltage source configuration. r 1 and r 2 allow the gain to be selected, while r 3 and r 4 shift the dac's output to a selected offset. note that r4 can be tied to v dd instead of v ss if a higher offset is desired. figure 8-5: digitally-controlled bipolar voltage source example circuit. equation 8-3: v out , v oa+ , and v o calculations r 1 v cc + v cc C v o i 2 c? 2-wire v ref optional mcp47febxx v dd v out r 2 c 1 r 3 v cc + v cc C r sense comp. v trip r 23 r 2 r 3 r 2 r 3 + ------------------- = v 23 v cc+ r 2 ?? v cc- r 3 ?? + r 2 r 3 + ------------------------------------------------------ = v trip v out r 23 v 23 r 1 + r 1 r 23 + -------------------------------------------- - = thevenin equivalent r 1 r 23 v 23 v out v trip v out = v ref g dac register value 2 n r 3 v cc + v cc C v o i 2 c? 2-wire v ref optional mcp47febxx v dd r 2 v out v in r 1 r 4 c 1 v oa+ v oa+ = v out r 4 r 3 + r 4 v out = v ref g dac register value 2 n v o = v oa+ (1 + ) - v dd ( ) r 2 r 1 r 2 r 1 downloaded from: http:///
? 2015 microchip technology inc. ds20005375a-page 75 mcp47febxx 8.5 selectable gain and offset bipolar voltage output in some applications, precision digital control of the output range is desirable. figure 8-6 illustrates how to use the dac devices to achieve this in a bipolar or single-supply application. this circuit is typically used for linearizing a sensor whose slope and offset varies. the equation to design a bipolar window dac would be utilized if r 3 , r 4 and r 5 are populated. 8.5.1 bipolar dac example an output step size of 1 mv, with an output range of 2.05v, is desired for a particular application. the equation can be simplified to: equation 8-4: equation 8-5: figure 8-6: bipolar voltage source with selectable gain and offset. equation 8-6: v out , v oa+ , and v o calculations equation 8-7: bipolar window dac using r 4 and r 5 step 1: calculate the range: +2.05v C (-2.05v) = 4.1v. step 2: calculate the resolution needed: 4.1v/1 mv = 4100 since 2 12 = 4096, 12-bit resolution is desired. step 3: the amplifier gain (r 2 /r 1 ), multiplied by full-scale v out (4.096v), must be equal to the desired minimum output to achieve bipo- lar operation. since any gain can be realized by choosing resistor values (r 1 +r 2 ), the v ref value must be selected first. if a v ref of 4.096v is used, solve for the amplifiers gain by setting the dac to 0, knowing that the output needs to be -2.05v. step 4: next, solve for r 3 and r 4 by setting the dac to 4096, knowing that the output needs to be +2.05v. r 2 C r 1 -------- - 2.05 C 4.096v ---------------- - = if r 1 = 20 k ? and r 2 = 10 k ? , the gain will be 0.5. r 2 r 1 ----- - 12 -- -= r 4 r 3 r 4 + ?? ----------------------- - 2.05v 0.5 4.096v ? ?? + 1.5 4.096v ? ------------------------------------------------------- 23 -- - == if r 4 = 20 k ? , then r 3 = 10 k ? r 3 v cc + v cc C v out i 2 c? 2-wire v ref optional mcp47febxx v dd r 2 v o v in r 1 r 4 c 1 r 5 optional v oa+ v cc + v cc C c 1 = 0.1 f offset adjust gain adjust v out = v ref g dac register value 2 n v oa+ = v out r 4 + v cc- r 5 r 3 + r 4 v o = v oa+ ( 1 + ) - v in ( ) r 2 r 1 r 2 r 1 thevenin equivalent v 45 v cc+ r 4 v cc- r 5 + r 4 r 5 + -------------------------------------------- - = v in+ v out r 45 v 45 r 3 + r 3 r 45 + -------------------------------------------- - = r 45 r 4 r 5 r 4 r 5 + ------------------- = v o v in+ 1 r 2 r 1 ----- - + ?? ?? v a r 2 r 1 ----- - ?? ?? C = offset adjust gain adjust downloaded from: http:///
mcp47febxx ds20005375a-page 76 ? 2015 microchip technology inc. 8.6 designing a double-precision dac figure 8-7 shows an example design of a single-supply voltage output capable of up to 24-bit resolution. this requires two 12-bit dacs. this design is simply a voltage divider with a buffered output. as an example, if a similar application to the one developed in section 8.5.1 bipolar dac example required a resolution of 1 v instead of 1 mv, and a range of 0v to 4.1v, then 12-bit resolution would not be adequate. figure 8-7: simple double precision dac using mcp47febx2. equation 8-8: v out calculation 8.7 building programmable current source figure 8-8 shows an example of building a programmable current source using a voltage follower. the current sensor resistor is used to convert the dac voltage output into a digitally-selectable current source. the smaller r sense is, the less power dissipated across it. however, this also reduces the resolution that the current can be controlled. figure 8-8: digitally-controlled current source. step 1: calculate the resolution needed: 4.1v/1 v = 4.1 x 10 6 . since 2 22 =4.2x10 6 , 22-bit resolution is desired. since dnl = 1.0 lsb, this design can be attempted with the 12-bit dac. step 2: since dac1s v out1 has a resolution of 1 mv, its output only needs to be pulled 1/1000 to meet the 1 v target. dividing v out0 by 1000 would allow the application to compensate for dac1s dnl error. step 3: if r 2 is 100 ? , then r 1 needs to be 100 k ? . step 4: the resulting transfer function is shown in the equation of example 8-8 . r 1 v cc + v cc C v out i 2 c? 2-wire v ref optional mcp47febx2 v dd i 2 c 2-wire v ref optional mcp47febx2 v dd r 2 0.1 f v out0 v out1 (dac0) (dac1) v out = gx = selected op amp gain v out0 * r 2 + v out1 * r 1 r 1 + r 2 v out0 = (v ref ? g ? dac0 register value)/4096 v out1 = (v ref ? g ? dac1 register value)/4096 where: r sense i b load i l v cc + v cc C v out i l v out r sense -------------- - ? ? 1+ ------------ - ? = i b i l ? ---- = ??? ? common-emitter current gain ? where v dd i 2 c? 2-wire v ref optional mcp47febxx v dd (or v ref ) downloaded from: http:///
? 2015 microchip technology inc. ds20005375a-page 77 mcp47febxx 8.8 serial interface communication times table 8-1 shows time/frequency of the supported operations of the i 2 c serial interface for the different serial interface operational frequencies. this, along with the v out output performance (such as slew rate), would be used to determine your applications volatile dac register update rate. table 8-1: serial interface times / frequencies command # of bit clocks ( 1 ) data update rate (8-bit/10-bit/12-bit) (data words/second) comments operation code hv mode ( 6 ) c 1 c 0 100 khz 400 khz 3.4 mhz ( 5 ) write command (normal and high- voltage) 00 ( 3 ) single 38 2,632 10,526 89,474 00 ( 3 ) continuous 27n + 11 3,559 14,235 120,996 for 10 data words read command (normal and high- voltage) ( 2 ) 11 ( 3 ) random 48 2,083 8,333 70,833 11 ( 3 ) continuous 18n + 11 4,762 19,048 161,905 for 10 data words 11 ( 3 ) last address 29 3,448 13,793 117,241 general call reset command ( 3 ) single 20 5,000 20,000 170,000 note 4 general call wake-up command ( 3 ) single 20 5,000 20,000 170,000 note 4 enable configuration bit (high-voltage) command 1 0 yes single 20 5,000 20,000 170,000 1 0 yes continuous 9n + 11 9,901 39,604 336,634 for 10 data words disable configuration bit (high-voltage) command 0 1 yes single 20 5,000 20,000 170,000 0 1 yes continuous 9n + 11 9,901 39,604 336,634 for 10 data words note 1: n indicates the number of times the command operation is to be repeated. 2: this command is useful to determine when an eeprom programming cycle has completed. 3: this command can be either normal voltage or high voltage. 4: determined by general call command byte after the i 2 c general call address. 5: there is a minimal overhead to enter into 3.4 mhz mode. 6: nonvolatile registers can only use the single mode. downloaded from: http:///
mcp47febxx ds20005375a-page 78 ? 2015 microchip technology inc. 8.9 software i 2 c interface reset sequence at times, it may become necessary to perform a software reset sequence to ensure the mcp47febxx device is in a correct and known i 2 c interface state. this technique only resets the i 2 c state machine. this is useful if the mcp47febxx device powers-up in an incorrect state (due to excessive bus noise, etc), or if the master device is reset during communication. figure 8-9 shows the communication sequence to software reset the device. figure 8-9: software reset sequence format. the 1 st start bit will cause the device to reset from a state in which it is expecting to receive data from the master device. in this mode, the device is monitoring the data bus in receive mode and can detect if the start bit forces an internal reset. the nine bits of 1 are used to force a reset of those devices that could not be reset by the previous start bit. this occurs only if the mcp47febxx is driving an a bit on the i 2 c bus, or is in output mode (from a read command) and is driving a data bit of 0 onto the i 2 c bus. in both of these cases, the previous start bit could not be generated due to the mcp47febxx holding the bus low. by sending out nine 1 bits, it is ensured that the device will see an a bit (the master device does not drive the i 2 c bus low to acknowledge the data sent by the mcp47febxx), which also forces the mcp47febxx to reset. the 2 nd start bit is sent to address the rare possibility of an erroneous write. this could occur if the master device was reset while sending a write command to the mcp47febxx, and then as the master device returns to normal operation and issues a start condi- tion, while the mcp47febxx is issuing an acknowl- edge. in this case, if the 2 nd start bit is not sent (and the stop bit was sent) the mcp47febxx could initiate a write cycle. the stop bit terminates the current i 2 c bus activity. the mcp47febxx waits to detect the next start condition. this sequence does not affect any other i 2 c devices which may be on the bus, as they should disregard this as an invalid command. 8.10 design considerations in the design of a system with the mcp47febxx devices, the following considerations should be taken into account: power supply considerations layout considerations 8.10.1 power supply considerations the typical application will require a bypass capacitor in order to filter high-frequency noise, which can be induced onto the power supply's traces. the bypass capacitor helps to minimize the effect of these noise sources on signal integrity. figure 8-10 illustrates an appropriate bypass strategy. in this example, the recommended bypass capacitor value is 0.1 f. this capacitor should be placed as close (within 4 mm) to the device power pin (v dd ) as possible. the power source supplying these devices should be as clean as possible. if the application circuit has separate digital and analog power supplies, v dd and v ss should reside on the analog plane. figure 8-10: typical microcontroller connections. note: this technique is documented in an1028. note: the potential for this erroneous write only occurs if the master device is reset while sending a write command to the mcp47febxx. s 1 1 1 1 1 1 1 1 s p start bit nine bits of 1 start bit stop bit v dd v dd v ss v ss mcp47febxx 0.1 f pic ? microcontroller 0.1 f scl v out v ref sda downloaded from: http:///
? 2015 microchip technology inc. ds20005375a-page 79 mcp47febxx 8.10.2 layout considerations several layout considerations may be applicable to your application. these may include: noise pcb area requirements 8.10.2.1 noise inductively-coupled ac transients and digital switching noise can degrade the input and output signal integrity, potentially masking the mcp47febxxs performance. careful board layout minimizes these effects and increases the signal-to-noise ratio (snr). multi-layer boards utilizing a low-inductance ground plane, isolated inputs, isolated outputs and proper decoupling are critical to achieving the performance that the silicon is capable of providing. particularly harsh environments may require shielding of critical signals. separate digital and analog ground planes are recommended. in this case, the v ss pin and the ground pins of the v dd capacitors should be terminated to the analog ground plane. 8.10.2.2 pcb area requirements in some applications, pcb area is a criteria for device selection. tab l e 8 - 2 shows the typical package dimensions and area for the different package options. note: breadboards and wire-wrapped boards are not recommended. table 8-2: package footprint ( 1 ) package package footprint pins type code dimensions (mm) area (mm 2 ) length width 8 tssop st 3.00 4.40 13.20 note 1: does not include recommended land pattern dimensions. dimensions are typical values. downloaded from: http:///
mcp47febxx ds20005375a-page 80 ? 2015 microchip technology inc. notes: downloaded from: http:///
? 2015 microchip technology inc. ds20005375a-page 81 mcp47febxx 9.0 development support development support can be classified into two groups. these are: development tools technical documentation 9.1 development tools several development tools are available to assist in your design and evaluation of the mcp47febxx devices. the currently available tools are shown in tab l e 9 - 1 . figure 9-1 shows how the tssop20ev bond-out pcb can be populated to easily evaluate the mcp47febxx devices. the 8-pin and 20-pin tssop packages have the same pin pitch (0.65 mm bsc) and package width (4.40 mm typ.), and the 8-pin tssop package can be placed on the 20-pin tssop footprint. device evalua- tion can use the pickit? serial analyzer to control the dac output registers and state of the configuration, control and status register. the tssop20ev boards may be purchased directly from the microchip web site at www.microchip.com . 9.2 technical documentation several additional technical documents are available to assist you in your design and development. these technical documents include application notes, technical briefs, and design guides. ta bl e 9 - 2 shows some of these documents. table 9-1: development tools ( note 1 ) board name part # comment 20-pin tssop and ssop evaluation board tssop20ev most flexible option - recommended bond-out pcb 14-pin soic/tssop/dip evaluation board soic14ev soic-8 evaluation board soic8ev note 1: supports the pickit? serial analyzer. see the users guide for additional information and requirements. table 9-2: technical documentation application note number title literature # an1326 using the mcp4728 12-bit dac for ldmos amplifier bias control applications ds01326 signal chain design guide ds21825 analog solutions for automotive applications design guide ds01005 downloaded from: http:///
mcp47febxx ds20005375a-page 82 ? 2015 microchip technology inc. figure 9-1: mcp47febxx evaluation board circuit using tssop20ev. 0 ? 4.7k ? 0 ? 47feb two blue wire jumpers to connect pickit ? serial interface (i 2 c?) to device pins 1x6 male header, with 90 right angle mcp47febxx-a0e/st installed in u3 (bottom 8 pins of tssop-20 footprint) connected to digital ground connected to digital power (v l ) plane v dd sda scl (dgnd) plane nc/v out1 lat/hvc v ss 1.0 f 4.7k ? v out0 v ref downloaded from: http:///
? 2015 microchip technology inc. ds20005375a-page 83 mcp47febxx 10.0 packaging information 10.1 package marking information 8-lead tssop (4.4 mm) example aaag e449 256 device number code device number code mcp47feb01a0-e/st aaag mcp47feb12a0-e/st aaal mcp47feb01a0t-e/st aaag mcp47feb12a0t-e/st aaal mcp47feb01a1-e/st aaau mcp47feb12a1-e/st aabg mcp47feb01a1t-e/st aaau mcp47feb12a1t-e/st aabg mcp47feb01a2-e/st aaav mcp47feb12a2-e/st aabh mcp47feb01a2t-e/st aaav mcp47feb12a2t-e/st aabh mcp47feb01a3-e/st aaaw mcp47feb12a3-e/st aabj mcp47feb01a3t-e/st aaaw mcp47feb12a3t-e/st aabj mcp47feb02a0-e/st aaak mcp47feb21a0-e/st aaaj mcp47feb02a0t-e/st aaak mcp47feb21a0t-e/st aaaj mcp47feb02a1-e/st aabd mcp47feb21a1-e/st aaba mcp47feb02a1t-e/st aabd mcp47feb21a1t-e/st aaba mcp47feb02a2-e/st aabe mcp47feb21a2-e/st aabb mcp47feb02a2t-e/st aabe mcp47feb21a2t-e/st aabb mcp47feb02a3-e/st aabf mcp47feb21a3-e/st aabc mcp47feb02a3t-e/st aabf mcp47feb21a3t-e/st aabc mcp47feb11a0-e/st aaah mcp47feb22a0-e/st aaam mcp47feb11a0t-e/st aaah mcp47feb22a0t-e/st aaam mcp47feb11a1-e/st aaax mcp47feb22a1-e/st aabk mcp47feb11a1t-e/st aaax mcp47feb22a1t-e/st aabk mcp47feb11a2-e/st aaay mcp47feb22a2-e/st aabl mcp47feb11a2t-e/st aaay mcp47feb22a2t-e/st aabl mcp47feb11a3-e/st aaaz mcp47feb22a3-e/st aabm mcp47feb11a3t-e/st aaaz mcp47feb22a3t-e/st aabm legend: xx...x customer-specific information y year code (last digit of calendar year) yy year code (last 2 digits of calendar year) ww week code (week of january 1 is week 01) nnn alphanumeric traceability code pb-free jedec ? designator for matte tin (sn) * this package is pb-free. the pb-free jedec designator ( ) can be found on the outer packaging for this package. note : in the event the full microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information. 3 e 3 e xyww downloaded from: http:///
mcp47febxx ds20005375a-page 84 ? 2015 microchip technology inc.

! "# !"#$%! & '(!%&! %(
%")%%%" &
"*"

%!"&
"$

% !

"$

% !

%#"+&& " , &
"%
*-+ ./0 . &

%#%!
))%
!%%
*10 $ &
'! !)%
!%%
'$
$
&%
!

"# 1
%&
%! %2" ) ' %
2$%

%"% %%033)))&

&32 4% 55* * &
5&% 6 67 8 6!&(
$ 6 9 % :+./ 7 ;% < <
""2 2 9 + %"
$$ + < + 7 ="% * :./
""2="% * , +
""25% , , 1
%5% 5 + : + 1
% % 5 *1 1
% > < 9> 5" 2 < 5"="% ( < , d n e e1 note 1 12 b e c a a1 a2 l1 l

) /9:. downloaded from: http:///
? 2015 microchip technology inc. ds20005375a-page 85 mcp47febxx noe: for the most current package drawings, please see the microchip packaging specification located at http://www.microchip.com/packaging downloaded from: http:///
mcp47febxx ds20005375a-page 86 ? 2015 microchip technology inc. notes: downloaded from: http:///
? 2015 microchip technology inc. ds20005375a-page 87 mcp47febxx appendix a: revision history revision a (february 2015) original release of this document. downloaded from: http:///
mcp47febxx ds20005375a-page 88 ? 2015 microchip technology inc. appendix b: i 2 c serial interface this i 2 c interface is a two-wire interface that allows multiple devices to be connected to this two-wire bus. figure b-1 shows a typical i 2 c interface connection. figure b-1: typical i 2 c interface. b.1 overview a device that sends data onto the bus is defined as transmitter, and a device receiving data is defined as receiver. the bus has to be controlled by a master device which generates the serial clock (scl), controls the bus access and generates the start and stop conditions. devices that do not generate a serial clock work as slave devices. both master and slave can operate as transmitter or receiver, but the master device determines which mode is activated. communication is initiated by the master (micro- controller), which sends the start bit followed by the slave address byte. the first byte transmitted is always the slave address byte, which contains the device code, the address bits and the r/w bit. the i 2 c interface specifies different communication bit rates. these are referred to as standard, fast or high- speed modes. the mcp47febxx supports these three modes. the clock rates (bit rate) of these modes are: standard mode: up to 100 khz (kbit/s) fast mode: up to 400 khz (kbit/s) high-speed mode (hs mode): up to 3.4 mhz (mbit/s) the i 2 c protocol supports two addressing modes: 7-bit slave addressing 10-bit slave addressing (allows more devices on i 2 c bus) only 7-bit slave addressing will be discussed in this section. the i 2 c serial protocol allows multiple master devices on the i 2 c bus. this is referred to as multi-master. for this, all master devices must support multi-master operation. in this configuration, all master devices mon- itor their communication. if they detect that they wish to transmit a bit that is a logic high but is detected as a logic low (some other master device driving), they get off the bus. that is, they stop their communication and continue to listen to determine if the communication is directed towards them. the i 2 c serial protocol only defines the field types, field lengths, timings, etc. of a frame. the frame content defines the behavior of the device. for details on the frame content (commands/data), refer to section 7.0 device commands . the i 2 c serial protocol does define some commands called general call addressing, which allows the master device to communicate to all slave devices on the i 2 c bus. scl scl slave sda sda master typical i 2 c? interface connections other devices note: refer to the nxp specification #um10204, rev. 03 19 june 2007 document for more details on the i 2 c specifications. downloaded from: http:///
? 2015 microchip technology inc. ds20005375a-page 89 mcp47febxx b.2 signal descriptions the i 2 c interface uses two pins (signals). these are: sda (serial data) scl (serial clock) b.2.1 serial data (sda) the serial data (sda) signal is the data signal of the device. the value on this pin is latched on the rising edge of the scl signal when the signal is an input. with the exception of the start (restart) and stop con- ditions, the high or low state of the sda pin can only change when the clock signal on the scl pin is low. during the high period of the clock, the sda pins value (high or low) must be stable. changes in the sda pins value while the scl pin is high will be interpreted as a start or a stop condition. b.2.2 serial clock (scl) the serial clock (scl) signal is the clock signal of the device. the rising edge of the scl signal latches the value on the sda pin. depending on the clock rate mode, the interface will display different characteristics. b.3 i 2 c operation b.3.1 i 2 c bit states and sequence figure b-8 shows the i 2 c transfer sequence, while figure b-7 shows the bit definitions. the serial clock is generated by the master. the following definitions are used for the bit states: start bit (s) data bit acknowledge (a) bit (driven low) / no acknowledge (a ) bit (not driven low) repeated start bit (sr) stop bit (p) b.3.1.1 start bit the start bit (see figure b-2 ) indicates the beginning of a data transfer sequence. the start bit is defined as the sda signal falling when the scl signal is high. figure b-2: start bit. b.3.1.2 data bit the sda signal may change state while the scl signal is low. while the scl signal is high, the sda signal must be stable (see figure b-3 ). figure b-3: data bit. b.3.1.3 acknowledge (a) bit the a bit (see figure b-4 ) is typically a response from the receiving device to the transmitting device. depending on the context of the transfer sequence, the a bit may indicate different things. typically, the slave device will supply an a response after the start bit and 8 data bits have been received. an a bit has the sda signal low, while the a bit has the sda signal high. figure b-4: acknowledge waveform. table b-1 shows some of the conditions where the slave device issues the a or not a (a ). if an error condition occurs (such as an a instead of a), then a start bit must be issued to reset the command state machine. sdascl s 1 st bit 2 nd bit table b-1: mcp47febxx a/a responses event acknowledge bit response comment general call a slave address valid a slave address not valid a communication during eeprom write cycle a after device has received address and command, and valid conditions for eeprom write bus collision n/a i 2 c? module resets, or a dont care if the colli- sion occurs on the masters start bit sdascl data bit 1 st bit 2 nd bit a 8 d0 9 sda scl downloaded from: http:///
mcp47febxx ds20005375a-page 90 ? 2015 microchip technology inc. b.3.1.4 repeated start bit the repeated start bit (see figure b-5 ) indicates the current master device wishes to continue communicating with the current slave device without releasing the i 2 c bus. the repeated start condition is the same as the start condition, except that the repeated start bit follows a start bit (with the data bits + a bit) and not a stop bit. the start bit is the beginning of a data transfer sequence and is defined as the sda signal falling when the scl signal is high. figure b-5: repeat start condition waveform. b.3.1.5 stop bit the stop bit (see figure b-6 ) indicates the end of the i 2 c data transfer sequence. the stop bit is defined as the sda signal rising when the scl signal is high. a stop bit should reset the i 2 c interface of the slave device. figure b-6: stop condition receive or transmit mode. b.3.2 clock stretching clock stretching is something that the receiving device can do, to allow additional time to respond to the data that has been received. b.3.3 aborting a transmission if any part of the i 2 c transmission does not meet the com- mand format, it is aborted. this can be intentionally accomplished with a start or stop condition. this is done so that noisy transmissions (usually an extra start or stop condition) are aborted before they corrupt the device. figure b-7: typical 8-bit i 2 c waveform format. figure b-8: i 2 c data states and bit sequence. note 1: a bus collision during the repeated start condition occurs if: sda is sampled low when scl goes from low to high. scl goes low before sda is asserted low. this may indicate that another master is attempting to transmit a data 1 . sda scl sr = repeated start 1st bit scl sda a/a p 1 st bit sdascl s 2 nd bit 3 rd bit 4 th bit 5 th bit 6 th bit 7 th bit 8 th bit p a/a scl sda start condition stop condition data allowed to change data or a valid downloaded from: http:///
? 2015 microchip technology inc. ds20005375a-page 91 mcp47febxx b.3.4 slope control as the device transitions from hs mode to fs mode, the slope control parameter will change from the hs specification to the fs specification. for fast (fs) and high-speed (hs) modes, the device has a spike suppression and a schmitt trigger at sda and scl inputs. b.3.5 device addressing the i 2 c slave address control byte is the first byte received following the start condition from the master device. this byte has 7-bits to specify the slave address and the read/write control bit. figure b-9 shows the i 2 c slave address byte format, which contains the seven address bits and a read/write (r/w ) bit. figure b-9: i 2 c slave address control byte. b.3.6 hs mode the i 2 c specification requires that a high-speed mode device must be activated to operate in high-speed (3.4 mbit/s) mode. this is done by the master sending a special address byte following the start bit. this byte is referred to as the high-speed master mode code (hsmmc). the device can now communicate at up to 3.4 mbit/s on sda and scl lines. the device will switch out of the hs mode on the next stop condition. the master code is sent as follows: 1. start condition (s) 2. high-speed master mode code ( 0000 1xxx ), the xxx bits are unique to the high-speed (hs) mode master. 3. no acknowledge (a ) after switching to the high-speed mode, the next transferred byte is the i 2 c control byte, which specifies the device to communicate with, and any number of data bytes plus acknowledgments. the master device can then either issue a repeated start bit to address a different device (at high-speed) or a stop bit to return to fast/standard bus speed. after the stop bit, any other master device (in a multi-master system) can arbitrate for the i 2 c bus. see figure b-10 for illustration of hs mode command sequence. for more information on the hs mode, or other i 2 c modes, please refer to the nxp i 2 c specification. b.3.6.1 slope control the slope control on the sda output is different between the fast/standard speed and the high-speed clock modes of the interface. b.3.6.2 pulse gobbler the pulse gobbler on the scl pin is automatically adjusted to suppress spikes < 10 ns during hs mode. figure b-10: hs mode sequence. start bit read/write bit address byte r/w ack acknowledge bit 7-bit slave address a6 a5 a4 a3 a2 a1 a0 s a 0 0 0 0 1 x x xb sr a slave address a /a data p s = start bit sr = repeated start bit a = acknowledge bit a = not acknowledge bit r/w = read/write bit r/w p = stop bit (stop condition terminates hs mode) f/s-mode hs-mode hs-mode continues f/s-mode sr a slave address r/w hs select byte control byte command/data byte(s) control byte downloaded from: http:///
mcp47febxx ds20005375a-page 92 ? 2015 microchip technology inc. b.3.7 general call the general call is a method that the master device can communicate with all other slave devices. in a multi-master application, the other master devices are operating in slave mode. the general call address has two documented formats. these are shown in figure b-11 . the i 2 c specification documents three 7-bit command bytes. the i 2 c specification does not allow 00000000 (00h) in the second byte. also 00000100 and 00000110 functionality is defined by the specification. lastly a data byte with a 1 in the lsb indicates a hardware general call. for details on the operation of the mcp47febxxs general call commands, see section 7.3 general call commands . figure b-11: general call formats. note: only one general call command per issue of the general call control byte. any additional general call commands are ignored and not acknowledged. 0 000 s 0000 x xxxx a xx0 ap general call address second byte 7-bit command reserved 7-bit commands (by i 2 c specification C nxp specification # um10204, rev. 03 19 june 2007) 0000 011 b - reset and write programmable part of slave address by hardware 0000 010 b - write programmable part of slave address by hardware 0000 000 b - not allowed the following is a hardware general call format 0 000 s 0000 x xxxx a xx1 a general call address second byte master address x xxxx xxx ap n occurrences of (data + a) this indicates a hardware general call downloaded from: http:///
? 2015 microchip technology inc. ds20005375a-page 93 mcp47febxx appendix c: terminology c.1 resolution the resolution is the number of dac output states that divide the full-scale range. for the 12-bit dac, the resolution is 2 12 , meaning the dac code ranges from 0 to 4095. c.2 least significant bit (lsb) this is the voltage difference between two successive codes. for a given output voltage range, it is divided by the resolution of the device ( equation c-1 ). the range may be v dd (or v ref ) to v ss (ideal), the dac register codes across the linear range of the output driver (measured 1), or full-scale to zero-scale (measured 2). equation c-1: lsb voltage calculation c.3 monotonic operation monotonic operation means that the devices output voltage (v out ) increases with every 1 code step (lsb) increment (from v ss to the dacs reference voltage (v dd or v ref )). figure c-1: v w (v out ). note: when there are 2 n resistors in the resistor ladder and 2 n tap points, the full scale dac register code is resistor element (1 lsb) from the source reference voltage (v dd or v ref ). v lsb(measured) = v out(@4000) - v out(@100) (4000 - 100) 2 n = 4096 (mcp47feb2x) = 1024 (mcp47feb1x) = 256 (mcp47feb0x) ideal v lsb(ideal) = or v dd 2 n v ref 2 n measured 1 v lsb = v out(@fs) - v out(@zs) 2 n - 1 measured 2 40h3fh 3eh 03h 02h 01h 00h wiper code voltage (v w ~= v out ) v w (@ tap) v s0 v s1 v s3 v s63 v s64 v w = v sn + v zs(@ tap 0) n = 0 n = ? downloaded from: http:///
mcp47febxx ds20005375a-page 94 ? 2015 microchip technology inc. c.4 full-scale error (e fs ) the full-scale error (see figure c-3 ) is the error on the v out pin relative to the expected v out voltage (theoretical) for the maximum device dac register code (code fffh for 12-bit, code 3ffh for 10-bit, and code ffh for 8-bit) (see equation c-2 ). the error is dependent on the resistive load on the v out pin (and where that load is tied to, such as v ss or v dd ). for loads (to v ss ) greater than specified, the full-scale error will be greater. the error in bits is determined by the theoretical voltage step size to give an error in lsb. equation c-2: full scale error c.5 zero-scale error (e zs ) the zero-scale error (see figure c-2 ) is the difference between the ideal and measured v out voltage with the dac register code equal to 000h ( equation c-3 ). the error is dependent on the resistive load on the v out pin (and where that load is tied to, such as v ss or v dd ). for loads (to v dd ) greater than specified, the zero scale error will be greater. the error in bits is determined by the theoretical voltage step size to give an error in lsb. equation c-3: zero scale error c.6 total unadjusted error (e t ) the total unadjusted error (e t ) is the difference between the ideal and measured v out voltage. typi- cally, calibration of the output voltage is implemented to improve system performance. the error in bits is determined by the theortical voltage step size to give an error in lsb. equation c-4 shows the total unadjusted error calculation equation c-4: total unadjusted error calculation e fs = v out(@fs) - v ideal(@fs) v lsb(ideal) where: e fs is expressed in lsb v out(@fs) is the v out voltage when the dac register code is at full scale. v ideal(@fs) is the ideal output voltage when the dac register code is at full scale. v lsb(ideal) is the theoretical voltage step size. e zs = v out(@zs) v lsb(ideal) where: e fs is expressed in lsb v out(@zs) is the v out voltage when the dac register code is at zero-scale. v lsb(ideal) is the theoretical voltage step size. where: e t is expressed in lsb. v out_actual(@code) = the measured dac output voltage at the specified code. v out_ideal(@code) = the calculated dac output voltage at the specified code. ( code * v lsb(ideal) ) v lsb(ideal) =v ref /# steps 12-bit = v ref /4096 10-bit = v ref /1024 8-bit = v ref /256 e t = ( v out_actual(@code) - v out_ideal(@code) ) v lsb(ideal) downloaded from: http:///
? 2015 microchip technology inc. ds20005375a-page 95 mcp47febxx c.7 offset error (e os ) the offset error is the delta voltage of the v out voltage from the ideal output voltage at the specified code. this code is specified where the output amplifier is in the linear operating range; for the mcp47febxx we specify code 100 (decimal). offset error does not include gain error. figure c-2 illustrates this. this error is expressed in mv. offset error can be neg- ative or positive. the offset error can be calibrated by software in application circuits. figure c-2: offset error (zero gain error). c.8 offset error drift (e osd ) the offset error drift is the variation in offset error due to a change in ambient temperature. the offset error drift is typically expressed in ppm/ o c or v/ o c. c.9 gain error (e g ) gain error is a calculation based on the ideal slope using the voltage boundaries for the linear range of the output driver (ex code 100 and code 4000) (see figure c-3 ). the gain error calculation nullifies the devices offset error. the gain error indicates how well the slope of the actual transfer function matches the slope of the ideal transfer function. the gain error is usually expressed as percent of full-scale range (% of fsr) or in lsb. fsr is the ideal full scale voltage of the dac (see equation c-5 ). figure c-3: gain error and full-scale error example. equation c-5: example gain error c.10 gain-error drift (e gd ) the gain-error drift is the variation in gain error due to a change in ambient temperature. the gain error drift is typically expressed in ppm/ o c (of full scale range). ideal transfer actual dac input code 0 zero-scale error (e zs ) offset function 100 4000 v out error (e os ) transfer function v out ideal transfer actual dac input code 0 full-scale error (e fs ) gain error (e g ) function 100 4000 4095 v ref transfer function (@ code = 4000) ideal transfer function shifted by offset error (crosses at start of defined linear range) where: e g is expressed in %of full-scale range (fsr) v out(@4000) = the measured dac output voltage at the specified code. v out_ideal(@4000) = the calculated dac output voltage at the specified code. ( 4000 * v lsb(ideal) ) v os = measured offset voltage. v full scale range = expected full-scale output value (such as the v ref voltage). e g = * 100 ( v out(@4000) - v os - v out_ideal(@4000) ) v full-scale range downloaded from: http:///
mcp47febxx ds20005375a-page 96 ? 2015 microchip technology inc. c.11 integral nonlinearity (inl) the integral nonlinearity (inl) error is the maximum deviation of an actual transfer function from an ideal transfer function (straight line) passing through the defined end-points of the dac transfer function (after offset and gain errors have been removed). in the mcp47febxx, inl is calculated using the defined end points, dac code 100 and code 4000. inl can be expressed as a percentage of full-scale range (fsr) or in lsb. inl is also called relative accuracy. equation c-6 shows how to calculate the inl error in lsb and figure c-4 shows an example of inl accuracy. positive inl means higher v out voltage than ideal. negative inl means lower v out voltage than ideal. equation c-6: inl error figure c-4: inl accuracy. c.12 differential nonlinearity (dnl) the differential nonlinearity (dnl) error (see figure c-5 ) is the measure of step size between codes in actual transfer function. the ideal step size between codes is 1 lsb. a dnl error of zero would imply that every code is exactly 1 lsb wide. if the dnl error is less than 1 lsb, the dac guarantees monotonic output and no missing codes. equation c-7 shows how to calculate the dnl error between any two adjacent codes in lsb. equation c-7: dnl error figure c-5: dnl accuracy. where: inl is expressed in lsb. v calc_ideal = code * v lsb(measured) + v os v out(code = n) = the measured dac output voltage with a given dac register code v lsb(measured) = for measured: (v out(4000) - v out(100) )/3900 v os = measured offset voltage. e inl = ( v out - v calc_ideal ) v lsb(measured) 010 001 000 analog output (lsb) dac input code 011 111 100 101 1 2 3 4 5 6 0 7 110 ideal transfer function actual transfer function inl = < -1 lsb inl = 0.5 lsb inl = - 1 lsb where: dnl is expressed in lsb. v out(code = n) = the measured dac output voltage with a given dac register code. v lsb(measured) = for measured: (v out(4000) - v out(100) )/3900 e dnl = - 1 ( v out(code = n+1) - v out(code = n) ) v lsb(measured) 010 001 000 analog output (lsb) dac input code 011 111 100 101 1 2 3 4 5 60 7 dnl = 2 lsb dnl = 0.5 lsb 110 ideal transfer function actual transfer function downloaded from: http:///
? 2015 microchip technology inc. ds20005375a-page 97 mcp47febxx c.13 settling time the settling time is the time delay required for the v out voltage to settle into its new output value. this time is measured from the start of code transition, to when the v out voltage is within the specified accuracy. in the mcp47febxx, the settling time is a measure of the time delay until the v out voltage reaches within 0.5 lsb of its final value, when the volatile dac register changes from 1/4 to 3/4 of the full-scale range (12-bit device: 400h to c00h). c.14 major-code transition glitch major-code transition glitch is the impulse energy injected into the dac analog output when the code in the dac register changes state. it is normally specified as the area of the glitch in nv-sec, and is measured when the digital code is changed by 1 lsb at the major carry transition (example: 011...111 to 100... 000 , or 100... 000 to 011 ... 111 ). c.15 digital feed-through the digital feed-through is the glitch that appears at the analog output caused by coupling from the digital input pins of the device. the area of the glitch is expressed in nv-sec and is measured with a full-scale change (example: all 0 s to all 1 s and vice versa) on the digital input pins. the digital feed-through is measured when the dac is not being written to the output register. c.16 -3 db bandwidth this is the frequency of the signal at the v ref pin that causes the voltage at the v out pin to fall -3 db value from a static value on the v ref pin. the output decreases due to the rc characteristics of the resistor ladder and the characteristics of the output buffer. c.17 power-supply sensitivity (pss) pss indicates how the output of the dac is affected by changes in the supply voltage. pss is the ratio of the change in v out to a change in v dd for mid-scale output of the dac. the v out is measured while the v dd is varied from 5.5v to 2.7v as a step (v ref voltage held constant), and expressed in %/%, which is the % change of the dac output voltage with respect to the % change of the v dd voltage. equation c-8: pss calculation c.18 power-supply rejection ratio (psrr) psrr indicates how the output of the dac is affected by changes in the supply voltage. psrr is the ratio of the change in v out to a change in v dd for full-scale output of the dac. the v out is measured while the v dd is varied +/- 10% (v ref voltage held constant), and expressed in db or v/v. c.19 v out temperature coefficient the v out temperature coefficient quantifies the error in the resistor ladders resistance ratio (dac register code value) and output buffer due to temperature drift. c.20 absolute temperature coefficient the absolute temperature coefficient quantifies the error in the end-to-end output voltage (nominal output voltage v out ) due to temperature drift. for a dac this error is typically not an issue due to the ratiometric aspect of the output. c.21 noise spectral density noise spectral density is a measurement of the devices internally generated random noise, and is characterized as a spectral density (voltage per hz). it is measured by loading the dac to the mid-scale value and measuring the noise at the v out pin. it is measured in nv/ hz. where: pss is expressed in % / %. v out(@5.5v) = the measured dac output voltage with v dd = 5.5v. v out(@2.7v) = the measured dac output voltage with v dd = 2.7v. pss = ( v out(@5.5v) - v out(@2.7v) ) / v out(@5.5v) ) (5.5v - 2.7v) / 5.5v downloaded from: http:///
mcp47febxx ds20005375a-page 98 ? 2015 microchip technology inc. notes: downloaded from: http:///
? 2015 microchip technology inc. ds20005375a-page 99 mcp47febxx product identification system to order or obtain information, e. g., on pricing or delivery, refer to the factory or the listed sales office . device: mcp47feb01:single-channel 8-bit nv dac with external + internal references mcp47feb02: dual-channel 8-bit nv dac with external + internal references mcp47feb11: single-channel 10-bit nv dac with external + internal references mcp47feb12: dual-channel 10-bit nv dac with external + internal references mcp47feb21:single-channel 12-bit nv dac with external + internal references mcp47feb22:dual-channel 12-bit nv dac with external + internal references address options: a0 = 1100000 i 2 c address. a1 = 1100001 i 2 c address. a2 = 1100010 i 2 c address. a3 = 1100011 i 2 c address. tape and reel: t = tape and reel blank = tube temperature range: e = -40c to +125c package: st = plastic thin shrink small outline package (tssop), 8-lead examples: a) mcp47feb01a0t-e/st: 8-bit v out resolution, i 2 c address 1100000 , tape and reel, extended temp., 8ld tssop pkg. b) mcp47feb01a3t-e/st: 8-bit v out resolution, i 2 c address 1100011 , tape and reel, extended temp., 8ld tssop pkg. a) mcp47feb11a0-e/st: 10-bit v out resolution, i 2 c address 1100000 , tube, extended temp., 8ld tssop pkg. b) mcp47feb11a3t-e/st: 10-bit v out resolution, i 2 c address 1100011 , tape and reel, extended temp., 8ld tssop pkg. a) mcp47feb21a0t-e/st: 12-bit v out resolution, i 2 c address 1100000 , tape and reel, extended temp., 8ld tssop pkg. b) mcp47feb21a3t-e/st: 12-bit v out resolution, i 2 c address 1100011 , tape and reel, extended temp., 8ld tssop pkg. part no. x xx address temperature range device /xx package options x tape and reel downloaded from: http:///
mcp47febxx ds20005375a-page 100 ? 2015 microchip technology inc. notes: downloaded from: http:///
? 2015 microchip technology inc. ds20005375a-page 101 information contained in this publication regarding device applications and the like is provided only for your convenience and may be superseded by updates. it is your responsibility to ensure that your application meets with your specifications. microchip makes no representations or warranties of any kind whether express or implied, written or oral, statutory or otherwise, related to the information, including but not limited to its condition, quality, performance, merchantability or fitness for purpose . microchip disclaims all liability arising from this information and its use. use of microchip devices in life support and/or safety applications is entirely at the buyers risk, and the buyer agrees to defend, indemnify and hold harmless microchip from any and all damages, claims, suits, or expenses resulting from such use. no licenses are conveyed, implicitly or otherwise, under any microchip intellectual property rights. trademarks the microchip name and logo, the microchip logo, dspic, flashflex, flexpwr, jukeblox, k ee l oq , k ee l oq logo, kleer, lancheck, medialb, most, most logo, mplab, optolyzer, pic, picstart, pic 32 logo, righttouch, spynic, sst, sst logo, superflash and uni/o are registered trademarks of microchip tec hnology incorporated in the u.s.a. and other countries. the embedded control solutions company and mtouch are registered trademarks of microchip technology incorporated in the u.s.a. analog-for-the-digital age, bodycom, chipkit, chipkit logo, codeguard, dspicdem, dspicdem.net, ecan, in-circuit serial programming, icsp, inter-chip connectivity, kleernet, kleernet logo, miwi, mpasm, mpf, mplab certified logo, mplib, mplink, multitrak, netdetach, omniscient code generation, picdem, picdem.net, pickit, pictail, righttouch logo, real ice, sqi, serial quad i/o, total endurance, tsharc, usbcheck, varisense, viewspan, wiperlock, wireless dna, and zena are trademarks of microchip technology incorporated in the u.s.a. and other countries. sqtp is a service mark of microchip technology incorporated in the u.s.a. silicon storage technology is a registered trademark of microchip technology inc. in other countries. gestic is a registered trademar ks of microchip technology germany ii gmbh & co. kg, a subsidiary of microchip technology inc., in other countries. all other trademarks mentioned herein are property of their respective companies. ? 2015, microchip technology incorporated, printed in the u.s.a., all rights reserved. isbn: 978-1-63277-087-5 note the following details of the code protection feature on microchip devices: microchip products meet the specification cont ained in their particular microchip data sheet. microchip believes that its family of products is one of the most secure families of its kind on the market today, when used i n the intended manner and under normal conditions. there are dishonest and possibly illegal methods used to breach the code protection feature. all of these methods, to our knowledge, require using the microchip products in a manner outside the operating specif ications contained in microchips data sheets. most likely, the person doing so is engaged in theft of intellectual property. microchip is willing to work with the customer who is concerned about the integrity of their code. neither microchip nor any other semiconduc tor manufacturer can guarantee the security of their code. code protection does not mean that we are guaranteeing the product as unbreakable. code protection is constantly evolving. we at microchip are co mmitted to continuously improvin g the code protection features of our products. attempts to break microchips code protection feature may be a violation of the digital millennium copyright act. if such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that act. microchip received iso/ts-16949:2009 certification for its worldwide headquarters, design and wafer fabrication facilities in chandler and tempe, arizona; gresham, oregon and design centers in california and india. the companys quality system processes and procedures are for its pic ? mcus and dspic ? dscs, k ee l oq ? code hopping devices, serial eeproms, microperipherals, nonvolatile memory an d analog products. in addition, microchips quality system for the design and manufacture of development systems is iso 9001:2000 certified. quality management s ystem certified by dnv == iso/ts 16949 == downloaded from: http:///
ds20005375a-page 102 ? 2015 microchip technology inc. americas corporate office 2355 west chandler blvd. chandler, az 85224-6199 tel: 480-792-7200 fax: 480-792-7277 technical support: http://www.microchip.com/ support web address: www.microchip.com atlanta duluth, ga tel: 678-957-9614 fax: 678-957-1455 austin, tx tel: 512-257-3370 boston westborough, ma tel: 774-760-0087 fax: 774-760-0088 chicago itasca, il tel: 630-285-0071 fax: 630-285-0075 cleveland independence, oh tel: 216-447-0464 fax: 216-447-0643 dallas addison, tx tel: 972-818-7423 fax: 972-818-2924 detroit novi, mi tel: 248-848-4000 houston, tx tel: 281-894-5983 indianapolis noblesville, in tel: 317-773-8323 fax: 317-773-5453 los angeles mission viejo, ca tel: 949-462-9523 fax: 949-462-9608 new york, ny tel: 631-435-6000 san jose, ca tel: 408-735-9110 canada - toronto tel: 905-673-0699 fax: 905-673-6509 asia/pacific asia pacific office suites 3707-14, 37th floor tower 6, the gateway harbour city, kowloon hong kong tel: 852-2943-5100 fax: 852-2401-3431 australia - sydney tel: 61-2-9868-6733 fax: 61-2-9868-6755 china - beijing tel: 86-10-8569-7000 fax: 86-10-8528-2104 china - chengdu tel: 86-28-8665-5511 fax: 86-28-8665-7889 china - chongqing tel: 86-23-8980-9588 fax: 86-23-8980-9500 china - dongguan tel: 86-769-8702-9880 china - hangzhou tel: 86-571-8792-8115 fax: 86-571-8792-8116 china - hong kong sar tel: 852-2943-5100 fax: 852-2401-3431 china - nanjing tel: 86-25-8473-2460 fax: 86-25-8473-2470 china - qingdao tel: 86-532-8502-7355 fax: 86-532-8502-7205 china - shanghai tel: 86-21-5407-5533 fax: 86-21-5407-5066 china - shenyang tel: 86-24-2334-2829 fax: 86-24-2334-2393 china - shenzhen tel: 86-755-8864-2200 fax: 86-755-8203-1760 china - wuhan tel: 86-27-5980-5300 fax: 86-27-5980-5118 china - xian tel: 86-29-8833-7252 fax: 86-29-8833-7256 asia/pacific china - xiamen tel: 86-592-2388138 fax: 86-592-2388130 china - zhuhai tel: 86-756-3210040 fax: 86-756-3210049 india - bangalore tel: 91-80-3090-4444 fax: 91-80-3090-4123 india - new delhi tel: 91-11-4160-8631 fax: 91-11-4160-8632 india - pune tel: 91-20-3019-1500 japan - osaka tel: 81-6-6152-7160 fax: 81-6-6152-9310 japan - tokyo tel: 81-3-6880- 3770 fax: 81-3-6880-3771 korea - daegu tel: 82-53-744-4301 fax: 82-53-744-4302 korea - seoul tel: 82-2-554-7200 fax: 82-2-558-5932 or 82-2-558-5934 malaysia - kuala lumpur tel: 60-3-6201-9857 fax: 60-3-6201-9859 malaysia - penang tel: 60-4-227-8870 fax: 60-4-227-4068 philippines - manila tel: 63-2-634-9065 fax: 63-2-634-9069 singapore tel: 65-6334-8870 fax: 65-6334-8850 taiwan - hsin chu tel: 886-3-5778-366 fax: 886-3-5770-955 taiwan - kaohsiung tel: 886-7-213-7828 taiwan - taipei tel: 886-2-2508-8600 fax: 886-2-2508-0102 thailand - bangkok tel: 66-2-694-1351 fax: 66-2-694-1350 europe austria - wels tel: 43-7242-2244-39 fax: 43-7242-2244-393 denmark - copenhagen tel: 45-4450-2828 fax: 45-4485-2829 france - paris tel: 33-1-69-53-63-20 fax: 33-1-69-30-90-79 germany - dusseldorf tel: 49-2129-3766400 germany - munich tel: 49-89-627-144-0 fax: 49-89-627-144-44 germany - pforzheim tel: 49-7231-424750 italy - milan tel: 39-0331-742611 fax: 39-0331-466781 italy - venice tel: 39-049-7625286 netherlands - drunen tel: 31-416-690399 fax: 31-416-690340 poland - warsaw tel: 48-22-3325737 spain - madrid tel: 34-91-708-08-90 fax: 34-91-708-08-91 sweden - stockholm tel: 46-8-5090-4654 uk - wokingham tel: 44-118-921-5800 fax: 44-118-921-5820 worldwide sales and service 01/27/15 downloaded from: http:///

▲Up To Search▲

Price & Availability of MCP47FEB02A0-EST

	To Download MCP47FEB02A0-EST Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .